• Proceedings of the Optical Society of Korea Conference
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• 2000.02a
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• pp.224-225
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• 2000

Transparent and hard materials such as sapphire are used for many industrial applications as optical windows, hard materials on mechanical contact against abrasion, and substrate materials for opto-electronic semiconductor devices such as blue LED and blue LD etc. The materials should be cut along the proper shapes possible to be used for each application. In case of blue LED, the blue LED wafer should be cut to thousands of blue LED pieces at the final stage of the manufacturing process. The process of cutting the wafer is usually divided into two steps. The wafer is scribed along the proper shapes in the first step. It is inserted between transparent flexible sheets for easy handling. And then, it is broken and split in the next step. Harder materials such as diamonds are usually used to scribe the wafer, while it has a problem of low depth of scribing and abrasion of the harder material itself. The low depth of scribing can induce failure in breaking the wafer along the scribed line. It was also known that the expensive diamond tip should be replaced frequently for the abrasion. (omitted)

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1510-1512
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• 2000

Due to the shrinking of the chip size and increasing of the complexity in the modern electronic devices. the defect of wafer are so important to decide the yield in the device process. The engineers has studied the wafer defects and the characteristics. They published lots of the experimental methods. I did an experiment the gettering effect of the defects due to the high temperature and the long time diffusion. Actually, As the thickness of the wafer backside polysilicon is thicker and the diffusion time is faster. the defects on the wafer are decreased. The polysilicon gram boundaries of the wafer backside played an important part as the defect gettering site.

• Transactions of the Korean Society of Mechanical Engineers
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• v.19 no.5
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• pp.1319-1332
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• 1995

Numerical analysis was performed to characterize the particle deposition behavior on a horizontal free-standing wafer with thermophoretic effect under the turbulent flow field. A low Reynolds number k-.epsilon. turbulence model was used to analyze the turbulent flow field around the wafer, and the temperature field for the calculation of the thermophoretic effect was predicted from the energy equation introducing the eddy diffusivity concept. The deposition mechanisms considered were convection, diffusion, sedimentation, turbulence and thermophoresis. For both the upper and lower surfaces of the wafer, the averaged particle deposition velocities and their radial distributions were calculated and compared with the laminar flow results and available experimental data. It was shown by the calculated averaged particle deposition velocities on the upper surface of the wafer that the deposition-free zone, where the deposition velocite is lower than 10$^{-5}$ cm/s, exists between 0.096 .mu.m and 1.6 .mu.m through the influence of thermophoresis with positive temperature difference of 10 K between the wafer and the ambient air. As for the calsulated local deposition velocities, for small particle sizes d$_{p}$<0.05 .mu.m, the deposition velocity is higher at the center of the wafer than at the wafer edge, whereas for particle size of d$_{p}$ = 2.0 .mu.m the deposition takes place mainly on the inside area of the wafer. Finally, an approximate model for calculating the deposition velocities was recommended and the calculated deposition velocity results were compared with the present numerical solutions, those of Schmidt et al.'s model and the experimental data of Opiolka et al.. It is shown by the comparison that the results of the recommended model agree better with the numerical solutions and Opiolka et al.'s data than those of Schmidt's simple model.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.323-323
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• 2010

Saw damage of crystalline silicon wafer is unavoidable factor. Usually, alkali treatment for removing the damage has been carried out as the saw damage removal (SDR) process for priming the alkali texture. It usually takes lots of time and energy to remove the sawed damages for solar grade crystalline silicon wafers We implemented two different mixed acidic solution treatments to obtain the improved surface structure of silicon wafer without much sacrifice of the silicon wafer thickness. At the first step, the silicon wafer was dipped into the mixed acidic solution of $HF:HNO_3$=1:2 ration for polished surface and at the second step, it was dipped into the diluted mixed acidic solution of $HF:HNO_3:H_2O$=7:3:10 ratio for porous structure. This double treatment to the silicon wafer brought lower reflectance (25% to 6%) and longer carrier lifetime ($0.15\;{\mu}s$ to $0.39\;{\mu}s$) comparing to the bare poly-crystalline silicon wafer. With optimizing the concentration ratio and the dilution ratio, we can not only effectively substitute the time consuming process of SDR to some extent but also skip plasma enhanced chemical vapor deposition (PECVD) process. Moreover, to conduct alkali texture for pyramidal structure on silicon wafer surface, we can use only nitric acid rich solution of the mixed acidic solution treatment instead of implementing SDR.

• Journal of the Korea Society for Simulation
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• v.8 no.3
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• pp.49-66
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• 1999

Semiconductor wafer fabrication is known to be one of the most complex manufacturing processes due to process intricacy, random yields, product diversity, and rapid changing technologies. In this study we are concerned with the impact of lot release and dispatching policies on the performance of semiconductor wafer fabrication facilities. We consider several semiconductor wafer fabrication environments according to the machine failure types such as no failure, normal MTBF, bottleneck with low MTBF, high randomness, and high MTBF cases. Lot release rules to be considered are Deterministic, Poisson process, WR(Workload Regulation), SA(Starvation Avoidance), and Multi-SA. These rules are combined with several dispatching rules such as FIFO (First In First Out), SRPT (Shortest Remaining Processing Time), and NING/M(smallest Number In Next Queue per Machine). We applied the combined policies to each of semiconductor wafer fabrication environments. These policies are assessed in terms of throughput and flow time. Basically Weins fabrication setup was used to make the simulation models. The simulation parameters were obtained through the preliminary simulation experiments. The key results throughout the simulation experiments is that Multi-SA and SA are the most robust rules, which give mostly good performance for any wafer fabrication environments when used with any dispatching rules. The more important result is that for each of wafer fabrication environments there exist the best and worst choices of lot release and dispatching policies. For example, the Poisson release rule results in the least throughput and largest flow time without regard to failure types and dispatching rules.

• Journal of the Semiconductor & Display Technology
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• v.5 no.2 s.15
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• pp.47-49
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• 2006

Various methods of making thin film is being used in semiconductor manufacturing process. The most common method in this field includes CVD(Chemical Vapor Deposition) and PVD(Physical Vapor Deposition). Thin film is deposited on both the backside and the frontside of wafers. The thin film deposited on the backside has poor thickness profile, and can contaminate wafers in the following processes. If wafers with the thin film remaining on the backside are immersed in batch type process tank, the thin film fall apart from the backside and contaminate the nearest wafer. Thus, it is necessary to etch the backside of the wafer selectively without etching the frontside, and chemical injection nozzle positioned under the wafer can perform the backside etching. In this study, the backside chemical injection nozzle with optimized chemical injection profile is built for single wafer tool. The evaluation of this nozzle, performed on $Si_3N_4$ layer deposited on the backside of the wafer, shows the etching rate uniformity of less than 5% at the etching rate of more than $1000{\AA}$.

• Journal of the Semiconductor & Display Technology
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• v.8 no.1
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• pp.1-5
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• 2009

Typically, single-wafer wet etching is done by dispensing chemical onto the front and back side of spin wafer. The wafer is fixed by a number of chuck pins, which obstruct the chemical flow and would result in the incomplete removal of the remaining film, which can become a source of contamination in the next process. In this paper, we introduce a novel design of wafer chuck, in which chuck pins are groupped into two and each group of pins fixes the substrate alternatively. Two groups of chuck pins fix the high-speed spin substrate with non contact method using a magnetic material. The actual process has been executed to observe the effectiveness of this new wafer chuck. It was found that the new wafer chuck performed better than the conventional wafer chuck for removing the remaining film from the bevel and edge side of substrate.

• Journal of the Korean institute of surface engineering
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• v.51 no.3
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• pp.185-190
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• 2018

Dopant-free silicon heterojunction solar cells using Transition Metal Oxide(TMO) such as Molybdenum Oxide($MoO_X$) and Vanadium Oxide($V_2O_X$) have been focused on to increase the work function of TMO in order to maximize the work function difference between TMO and n-Si for a high-efficiency solar cell. One another way to increase the work function difference is to control the silicon wafer resistivity. In this paper, dopant-free silicon heterojunction solar cells were fabricated using the wafer with the various resistivity and analyzed to understand the effect of n-Si work function. As a result, it is shown that the high passivation and junction quality when $V_2O_X$ deposited on the wafer with low work function compared to the high work function wafer, inducing the increase of higher collection probability, especially at long wavelength region. the solar cell efficiency of 15.28% was measured in low work function wafer, which is 34% higher value than the high work function solar cells.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.176-180
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• 2001

There are several factors causing re-work in CMP process such as improper polish time calculation by operator. removal rate decline of the polisher, unstable in-suit pad conditioning, slurry supply module problem and wafer carrier rotation inconsistancy. And conclusively those fundimental reason for the re-work rate increasement is mainly from the cycle time delay between wafer polish and post measurement. Therefore, Wafer thickness measurement in wet condition could be able to remove those improper process conditions which may happen during the process in comparison with the conventional dried wafer measurement system and it can be able to reduce the CMP process cycle time. CMP scrap reduction by overpolish, re-work rate reduction, thickness control efficiency also can be easily achieved. CMP Equipment manufacturer also trying to develop integrated system which has multi-head & platen, cleaner, pre & post thickness measure and even control the polish time from the calculated removal rate of each polishing head by software. CMP re-work problem such as over & under polish by target thickness may result in the cycle time delay. By reducing those inefficient factors during the process and establish of the automatic process control, CLC system need to be adopted to maximize the process performance. Wafer to Wafer Polish Time Feed Back Control by measuring the wafer right after the polish shorten the polish time calculation for the next wafer and it lead to the perfact Post CMP target thickness control capability. By Monitoring all of the processed the wafer, CMP process will also be stabilize itself.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.176-180
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• 2001

There are several factors causing re-work in CMP process such as improper polish time calculation by operator, removal rate decline of the polisher, unstable in-suit pad conditioning, slurry supply module problem and wafer carrier rotation inconsistency. And conclusively those fundimental reason for the re-work rate increasement is mainly from the cycle time delay between wafer polish and post measurement. Therefore, Wafer thickness measurement in wet condition could be able to remove those improper process conditions which may happen during the process in comparison with the conventional dried wafer measurement system and it can be able to reduce the CMP process cycle time. CMP scrap reduction by overpolish, re-work rate reduction, thickness control efficiency also can be easily achieved. CMP Equipment manufacturer also trying to develop integrated system which has multi-head & platen, cleaner, pre & post thickness measure and even control the polish time from the calculated removal rate of each polishing head by software. CMP re-work problem such as over & under polish by target thickness may result in the cycle time delay. By reducing those inefficient factors during the process and establish of the automatic process control, CLC system need to be adopted to maximize the process performance. Wafer to Wafer Polish Time Feed Back Control by measuring the wafer right after the polish shorten the polish time calculation for the next wafer and it lead to the perfect Post CMP target thickness control capability. By Monitoring all of the processed the wafer, CMP process will also be stabilize itself.