• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2000년도 춘계학술대회 논문집
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• pp.743-746
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• 2000

The removal of contaminants of silicon wafers has been investigated by various methods. Laser cleaning is the new dry cleaning technique to replace wafer wet cleaning in the near future. A dry laser cleaning uses inert gas jet to remove contaminant particles lifted off by the action of a KrF excimer laser. A laser cleaning model is developed to simulate the cleaning process and analyze the influence of contaminant particles and experimental parameters on laser cleaning efficiency. The model demonstrates that various types of submicrometer-sized particles from the front sides of silicon wafer can be efficiently removed by laser cleaning. The laser cleaning is explained by a particle adhesion model. including van der Waals forces and hydrogen bonding, and a particle removal model involving rapid thermal expansion of the substrate due to the thermoelastic effect. In addition, the experiment of wafer laser cleaning using KrF excimer laser was conducted to remove various contaminant particles.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2000년도 춘계학술대회 논문집
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• pp.854-857
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• 2000

Chemical Mechanical Polishing(CMP) has been accepted as one of the essential processes for VLSI fabrication. However, as the polishing process continues, pad pores get to be glazed by polishing residues, which hinder the supply of new slurry. This defect makes removal rate decrease with a number of polished wafer and the desired within-chip planarity, within wafer and wafer-to-wafer nonuniformity are unable to be achieved. So, pad conditioning is essential to overcome this defect. The eletroplated diamond grit disk is used as the conventional conditioner, And alumina long fiber, the .jet power of high pressure deionized water and vacuum compression are under investigation. But, these methods have the defects like scratches on wafer surface by out of diamond grits, subsidences of pad pores by over-conditioning, and the limits of conditioning effect. To improve these conditioning methods. this paper presents the Characteristics of Ultrasonic conditioning aided by cavitation.

• 한국CDE학회논문집
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• 제22권1호
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• pp.1-9
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• 2017

This research develops dispatching rule for a wafer FABs with dedication constraints. Dedication, mostly considered in a photolithography step, is a feature in a modern FABs in order to increase the yield of machines and achieve the advance of manufacturing technology. However, the dedication has the critical problem because it causes dedication load of machines to unbalance. In this paper, we proposes the dedication load based dispatching rule for load balancing in order to resolve the problem. The objective of this paper is to balance dedication load of photo machines in wafer FABs with dedication constraint. Simulation experiments show that the proposed rule improves the performance of wafer FABs as well as load balance for dedication machines compared to open-loop control based conventional dispatching rule.

• 한국진공학회지
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• 제17권2호
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• pp.165-169
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• 2008

반도체 소자공정에서 균일한 두께의 금속박막을 증착하는 것은 매우 중요하다. 기존의 기판고정식 sputtering 장비로 증착한 indium tin oxide(ITO)박막의 두께 균일도가 $\pm4%\sim\pm5%$ 정도로 중앙부분이 더 두껍다. 방전전극 구조물을 설계하고 제작하여 sputtering되는 물질의 방향을 조절하였다. 개량된 sputtering gun을 사용하여 기판고정식 sputtering 장비에서 4" wafer 내에서 $\pm0.8\sim1.3%$ 정도로 두께 균일도를 증가시켰다. wafer to wafer에서는 $\pm$5.3%에서 $\pm$1.5%로 두께 균일도가 향상되었다. Al박막의 경우 $\pm$1.0% 이내의 두께 균일도를 얻을 수 있었다.

• 한국정밀공학회지
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• 제29권3호
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• pp.289-294
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• 2012

There are several indicators to represent characteristics of chemical mechanical planarization (CMP) such as material removal rate (MRR), surface quality and removal uniformity on a wafer surface. Especially, the removal uniformity on the wafer edge is one of the most important issues since it gives a significant impact on the yield of chip production on a wafer. Non-uniform removal rate at the wafer edge (edge effect) is mainly induced by a non-uniform pressure from nonuniform pad curvature during CMP process, resulting in edge exclusion which means the region that cannot be made to a chip. For this reason, authors tried to minimize the edge exclusion by using an edge profile control (EPC) ring. The EPC ring is equipped on the polishing head with the wafer to protect a wafer from the edge effect. Experimental results showed that the EPC ring could dramatically minimize the edge exclusion of the wafer. This study shows a possibility to improve the yield of chip production without special design changes of the CMP equipment.

• 반도체디스플레이기술학회지
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• 제22권4호
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• pp.66-71
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• 2023

This paper describes a hybrid cleaning method of silicon wafer combining nano-bubble and ultrasound to remove sub-micron particles and contaminants with minimal damage to the wafer surface. In the megasonic cleaning process of semiconductor manufacturing, the cavitation induced by ultrasound can oscillate and collapse violently often with re-entrant jet formation leading to surface damage. The smaller size of cavitation bubbles leads to more stable oscillations with more thermal and viscous damping, thus to less erosive surface cleaning. In this study, ultrasonic energy was applied to the wafer surface in the DI water to excite nano-bubbles at resonance to remove contaminant particles from the surface. A patented nano-bubble generator was developed for the generation of nano-bubbles with concentration of 1×10⁹ bubbles/ml and nominal nano-bubble diameter of 150 nm. Ultrasonic nano-bubble technology improved a contaminant removal efficiency more than 97% for artificial nano-sized particles of alumina and Latex with significant reduction in cleaning time without damage to the wafer surface.

• 한국산업보건학회지
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• 제26권1호
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• pp.1-10
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• 2016

Objectives: The aim of this study is to review the results of exposure to chemicals and to extremely low frequency(ELF) magnetic fields generated in wafer fabrication operations in the semiconductor industry. Methods: Exposure assessment studies of silicon wafer fab operations in the semiconductor industry were collected through an extensive literature review of articles reported until the end of 2015. The key words used in the literature search were "semiconductor industry", "wafer fab", "silicon wafer", and "clean room," both singly and in combination. Literature reporting on airborne chemicals and extremely low frequency(ELF) magnetic fields were collected and reviewed. Results and Conclusions: Major airborne hazardous agents assessed were several organic solvents and ethylene glycol ethers from Photolithography, arsenic from ion implantation and extremely low frequency magnetic fields from the overall fabrication processes. Most exposures to chemicals reported were found to be far below permissible exposure limits(PEL) (10% < PEL). Most of these results were from operators who handled processes in a well-controlled environment. In conclusion, we found a lack of results on exposure to hazardous agents, including chemicals and radiation, which are insufficient for use in the estimation of past exposure. The results we reviewed should be applied with great caution to associate chronic health effects.

• 제어로봇시스템학회논문지
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• 제6권9호
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• pp.831-835
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• 2000

The uniformity of themperature on a wafer is a wafer is one the most important parameters to conterol the RTF(Rapid Thermal Process) with proper input signals. It is impossible to achieve the uniformity of temperature without the exact estimation of temperature ar all points on the wafer. There fore, it is difficult to understand the internal dynamics as well as the structural complexities of the RTP, which is aprimary obstacle to measure the distributed temperatures on the wafer accurately. Furthermore, it is also hard to accomplish desirable estimation because only a few pyrometers are available in the general equipments. In the paper, a thermal model based on the chamber grometry of the AST SHS200 RTP system is developed to effectively control the thermal uniformity on the wafer. First of all, the estimation method of one-point measurement is developed, which is properly extended to the case of multi-point measurements. This thermal model is validated through simulation and experiments. The proposed work can be utilized to building a run-by -run or a real-time control of the RTP.

• 제어로봇시스템학회논문지
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• 제6권6호
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• pp.486-491
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• 2000

The dicing process cuts a semiconductor wafer to lengthwise and crosswise direction by using a rotating circular diamond blade. But inferior goods are made under the influence of several parameters in dicing such as blade, wafer, cutting water and cutting conditions. This paper describes a monitoring algorithm using neural network in order to find out an instant of vibration signal change when bad dicing appears. The algorithm is composed of two steps: feature extraction and decision. In the feature extraction, five features processed from vibration signal which is acquired by accelerometer attached on blade head are proposed. In the decision, back-propagation neural network is adopted to classify the dicing process into normal and abnormal dicing, and normal and damaged blade. Experiments have been performed for GaAs semiconductor wafer in the case of normal/abnormal dicing and normal/damaged blade. Based upon observation of the experimental results, the proposed scheme shown has a good accuracy of classification performance by which the inferior goods decreased from 35.2% to 6.5%.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2000년도 추계학술대회논문집B
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• pp.261-266
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• 2000

Temperature variation during silicon wafer baking is mainly due to natural convection caused by temperature difference between silicon wafer and upper plate. Several cases are tested and calculated numerically to improve temperature uniformity. The temperature difference and velocity magnitude in the flow cell is reduced for a small gap between the wafer and upper plate because the natural convection force is suppressed in the small space. The uniform temperature distribution can be obtained with controling the incoming flow distribution from the upper plate. An alternative method is the adiabatic wall condition on the upper plate to maintain the temperature uniformity within $0.3^{\circ}C$ on the water plate.