• 센서학회지
• /
• 제15권5호
• /
• pp.341-346
• /
• 2006

We have fabricated SOI CMOS active pixel image sensor with the pinned photodiode on handle wafer in order to reduce dark currents and improve spectral response. The structure of the active pixel image sensor is 4 transistors APS which consists of a reset and source follower transistor on seed wafer, and is comprised of the photodiode, transfer gate, and floating diffusion on handle wafer. The source of dark current caused by the interface traps located on the surface of a photodiode is able to be eliminated, as we apply the pinned photodiode. The source of dark currents between shallow trench isolation and the depletion region of a photodiode can be also eliminated by the planner process of the hybrid bulk/SOI structure. The photodiode could be optimized for better spectral response because the process of a photodiode on handle wafer is independent of that of transistors on seed wafer. The dark current was about 6 pA at 3.3 V of floating diffusion voltage in the case of transfer gate TX = 0 V and TX=3.3 V, respectively. The spectral response of the pinned photodiode was observed flat in the wavelength range from green to red.

• 반도체디스플레이기술학회지
• /
• 제5권2호
• /
• pp.41-46
• /
• 2006

Wet etching process in recent semiconductor manufacturing is devided into batch and single wafer type. Batch type wet etching process provides more throughput with poor etching uniformity compared to single wafer type process. Single wafer process achieves better etching uniformity by boom-swing injected chemical on rotating wafer. In this study, etching characteristics of $SiO_2$ layer at room and elevated temperature is evaluated and compared. The difference in etching rate and uniformity of each condition is identified, and the temperature profile of injected chemical is theoretically calculated and compared to that of experimental result. Better etching uniformity is observed with single wafer tool with boom-swing injection compared to single wafer process without boom-swing or batch type tool.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2002년도 춘계학술대회 논문집 유기절연재료 전자세라믹 방전플라즈마 일렉트렛트 및 응용기술
• /
• pp.223-227
• /
• 2002

As the channel length of device shrinks below $0.13{\mu}m$, CMP(chemical mechanical polishing) process got into key process for global planarization in the chip manufacturing process. The removal rate and non-uniformity of the CMP characteristics occupy an important position to CMP process control. Especially, the post-CMP thickness variation depends on the device yield as well as the stability of subsequent process. In this paper, every wafer polished two times for the improvement of oxide CMP process characteristics. Then, we discussed the removal rate and non-uniformity characteristics of post-CMP process. As a result of CMP experiment, we have obtained within-wafer non-uniformity (WIWNU) below 4 [%], and wafer-to-wafer non-uniformity (WTWNU) within 3.5 [%]. It is very good result, because the reliable non-uniformity of CMP process is within 5 [%].

• 한국정밀공학회지
• /
• 제34권2호
• /
• pp.107-114
• /
• 2017

In this investigation, we describe a metrological technique for surface and thickness profiles of a silicon (Si) wafer by using a 6 degree of freedom (DOF) stitching method. Low coherence scanning interferometry employing near infrared light, partially transparent to a Si wafer, is adopted to simultaneously measure the surface and thickness profiles of the wafer. For the large field of view, a stitching method of the sub-aperture measurement is added to the measurement system; also, 6 DOF parameters, including the lateral positioning errors and the rotational error, are considered. In the experiment, surface profiles of a double-sided polished wafer with a 100 mm diameter were measured with the sub-aperture of an 18 mm diameter at $10\times10$ locations and the surface profiles of both sides were stitched with the sub-aperture maps. As a result, the nominal thickness of the wafer was $483.2{\mu}m$ and the calculated PV values of both surfaces were $16.57{\mu}m$ and $17.12{\mu}m$, respectively.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
• /
• pp.341-344
• /
• 2006

LED chips are produced by cutting the sapphire on which GaN is evaporated. To cut the sapphire wafer into each LED chip, at first the wafer is scribed by diamond tool. To get the sharp groove shape for the nice cutting plane it is important the diamond tool shape, load, etc when the wafer is scribed. Here we tried to simulate the scribing process and get the scribing condition to reduce the wear rate of diamond tool for the sharp groove shape.

• 제어로봇시스템학회:학술대회논문집
• /
• 제어로봇시스템학회 2002년도 ICCAS
• /
• pp.55.4-55
• /
• 2002

In the semiconductor fabrication, particle contamination is wide-spread and one of major causes to yield loss. Extensive testing has revealed that even careful handling of wafers during processing may cause photo-resist materials to flake off wafer edges. So, to remove the photo-resist at the outer 5mm of wafers, UV(Ultraviolet) rays are exposed. WEE (Wafer Edge Exposure) process station is the system that exposes the wafer edge as prespecified by controlling the positioning mechanism and maintaining the light intensity level In this work, WEE process station has been designed so as to significantly lower the amount of particle contamination which occurs even during the most r...

• 한국재료학회지
• /
• 제8권10호
• /
• pp.890-897
• /
• 1998

n-InP(001)기판과 PECVD법으로 ${Si}_3N_4$(200nm)막이 성장된 InP 기판사이의 direct wafer bonding을 분석하였다. 두 기판을 접촉시켰을 때 이들 사이의 결합력에 크게 영향을 주는 표면 상태를 접촉각 측정과 AFM을 통해서 분석하였다. InP 기판은 $50{\%}$ 불산용액으로 에칭하였을 때 접촉각이 $5^{\circ}$, RMS roughness는 $1.54{\AA}$이었다. ${Si}_3N_4$는 암모니아수 용액으로 에칭하였을 때 RMS roughness가 $3.11{\AA}$이었다. Inp 기판과 ${Si}_3N_4$/InP를 각각 $50{\%}$ 불산 용액과 암모니아수 용액에 에칭한 후 접촉시켰을 때 상당한 크기의 초기 겹합력을 관찰할 수 있었다. 기계적으로 결합된 시편을 $580^{\circ}C$-$680^{\circ}C$, 1시간동안 수소 분위기와 질소분우기에서 열처리하였다. SAT(Scanning Acoustic Tomography)측정으로 두 기판 사이의 결합여부를 확인하였다. shear force로 측정한 InP 기판과 ${Si}_3N_4$/InP사이의 결합력은 ${Si}_3N_4$/InP 계면의 결합력만큼 증가되었다. TEM과 AES를 이용해서 di-rect water bonding 계면과 PECVD계면을 분석하였다.

• 마이크로전자및패키징학회지
• /
• 제20권3호
• /
• pp.71-74
• /
• 2013

본 연구에서는 웨이퍼 레벨 적층 과정에서 발생하는 웨이퍼 오정렬(misalignment) 현상과 웨이퍼 휘어짐(warpage)과의 관계에 대해서 조사하였다. $0.5{\mu}m$ 두께의 구리 박막 증착을 통해 최대 $45{\mu}m$의 휨 크기(bow height)를 갖는 웨이퍼를 제작하였으며, 이 휘어진 웨이퍼와 일반 웨이퍼를 본딩하였을 때 $6{\sim}15{\mu}m$ 정도의 정렬 오차가 발생하였다. 이는 약 $5{\mu}m$의 웨이퍼 확장(expansion)과 약 $10{\mu}m$의 미끄러짐(slip)의 복합 거동으로 설명할 수 있으며, 웨이퍼 휘어짐의 경우 확장 오정렬보다 본딩 과정에서의 미끄러짐 오정렬에 주로 기여하는 것으로 보인다.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2004년도 하계학술대회 논문집 C
• /
• pp.1820-1822
• /
• 2004

In this study, major research fields are classified as ozone generation system for dry cleaning wafer of etched silicon wafer, dry cleaning process of etched silicon wafer which includes SEM analysis and ESCA analysis. The following results are deduced from each experiment and analysis. The magnitudes of carbon and silicon were similar to the survey spectrum of silicon wafer which does not cleaning, but magnitude of oxygen was much bigger Because UV light activates oxygen molecules in the oxide film on the silicon wafer.

• 유공압시스템학회논문집
• /
• 제8권3호
• /
• pp.14-20
• /
• 2011

This study aims at aligning multiple wafers to reduce wafer handling time in wafer processes. We designed a multilevel structure for a prealigner which can handle multiple wafer simultaneously in a system. The system consists of gripping parts, kinematic parts, vacuum chucks, pneumatic units, hall sensors and a DSP controller. Aligning procedure has two steps: mechanical gripping and notch finding. In the first step, a wafer is aligned in XY directions using 4-point mechanical contact. The rotational error can be found by detecting a signal in a notch using hall sensors. A dual prealigner was designed for 300mm wafers and constructed for a performance test. The accuracy was monitored by checking the movement of a notch in a machine vision. The result shows that the dual prealigner has enough performance as commercial products.