• 제목/요약/키워드: Wafer thickness

검색결과 465건 처리시간 0.031초

Effects of oxide layer formed on TiN coated silicon wafer on the friction characteristics

  • Cho, C.W.;Lee, Y.Z.
    • 한국윤활학회:학술대회논문집
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    • 한국윤활학회 2002년도 proceedings of the second asia international conference on tribology
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    • pp.167-168
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    • 2002
  • In this study, the effects of oxide layer formed on the wear tracks of TiN coated silicon wafer on friction characteristics were investigated. Silicon wafer was used for the substrate of coated disk specimens, which were prepared by depositing TiN coating with $1\;{\mu}m$ in coating thickness. AISI 52100 steel balls were used for the counterpart. The tests were performed both in air for forming oxide layer on the wear track and in nitrogen to avoid oxidation. This paper reports characterization of the oxide layer effects on friction characteristics using X-ray diffraction (XRD). scanning electron microscopy (SEM) and friction force microscope (FFM).

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고온 확산공정에 따른 산화막의 전기적 특성 (Electrical Characteristics of Oxide Layer Due to High Temperature Diffusion Process)

  • 홍능표;홍진웅
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제52권10호
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    • pp.451-457
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    • 2003
  • The silicon wafer is stable status at room temperature, but it is weak at high temperatures which is necessary for it to be fabricated into a power semiconductor device. During thermal diffusion processing, a high temperature produces a variety thermal stress to the wafer, resulting in device failure mode which can cause unwanted oxide charge or some defect. This disrupts the silicon crystal structure and permanently degrades the electrical and physical characteristics of the wafer. In this paper, the electrical characteristics of a single oxide layer due to high temperature diffusion process, wafer resistivity and thickness of polyback was researched. The oxide quality was examined through capacitance-voltage characteristics, defect density and BMD(Bulk Micro Defect) density. It will describe the capacitance-voltage characteristics of the single oxide layer by semiconductor process and device simulation.

Flexible 마이크로시스템을 위한 압전 박막 공진기의 설계 및 제작 (Design and fabrication of film Bulk Acoustic Resonator for flexible Microsystems)

  • 강유리;김용국;김수원;주병권
    • 한국전기전자재료학회논문지
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    • 제16권12S호
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    • pp.1224-1231
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    • 2003
  • This paper reports on the air-gap type thin film bulk acoustic wave resonator(FBAR) using ultra thin wafer with thickness of 50$\mu\textrm{m}$. It was fabricated to realize a small size devices and integrated objects using MEMS technology for flexible microsystems. To reduce a error of experiment, MATLAB simulation was executed using material characteristic coefficient. Fabricated thin FBAR consisted of piezoelectric film sandwiched between metal electrodes. Used piezoelectric film was the aluminum nitride(AlN) and electrode was the molybdenum(Mo). Thin wafer was fabricated by wet etching and dry etching, and then handling wafer was used to prevent damage of FBAR. The series resonance frequency and the parallel frequency measured were 2.447㎓ and 2.487㎓, respectively. Active area is 100${\times}$100$\mu\textrm{m}$$^2$.Q-factor was 996.68 and K$^2$$\_$eff/ was 3.91%.

태양전지 실리콘 웨이퍼를 위한 실험계획법 기반 근적외선 광학계의 최적조건 선정 (Optimal Parameter Selection of Near-Infrared Optics Based Design of Experiment for Silicon Wafer in Solar Cell)

  • 서형준;김경범
    • 반도체디스플레이기술학회지
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    • 제12권3호
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    • pp.29-34
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    • 2013
  • Solar cell has been considered as renewable green energy. Its silicon wafer thickness is thinner due to manufacturing cost and accordingly micro cracks is often generated in the process. Micro cracks result in bad quality of solar cell, and so their accurate and reliable detection is required. In this paper, near-infrared optics system is newly designed based on the analysis of near-infrared transmittance characteristics and its important parameters are optimally selected using the design of experiment for micro crack detection in solar cell wafer. The performance of the proposed method is verified using several experiments.

박형 결정질 실리콘 태양전지에서의 휨현상 감소를 위한 알루미늄층 두께 조절 (Bow Reduction in Thin Crystalline Silicon Solar Cell with Control of Rear Aluminum Layer Thickness)

  • 백태현;홍지화;임기조;강기환;유권종;송희은
    • 한국태양에너지학회:학술대회논문집
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    • 한국태양에너지학회 2012년도 춘계학술발표대회 논문집
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    • pp.108-112
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    • 2012
  • Crystalline silicon solar cell remains the major player in the photovoltaic marketplace with 90 % of the market, despite the development of a variety of thin film technologies. Silicon's excellent efficiency, stability, material abundance and low toxicity have helped to maintain its position of dominance. However, the cost of silicon photovoltaic remains a major barrier to reducing the cost of silicon photovoltaics. Using the crystalline silicon wafer with thinner thickness is the promising way for cost and material reduction in the solar cell production. However, the thinner thickness of silicon wafer is, the worse bow phenomenon is induced. The bow phenomenon is observed when two or more layers of materials of different temperature expansion coefficiencies are in contact, in this case silicon and aluminum. In this paper, the solar cells were fabricated with different thicknesses of Al layer in order to reduce the bow phenomenon. With lower paste applications, we observed that the bow could be reduced by up to 40% of the largest value with 130 micron thickness of the wafer even though the conversion efficiency decrease of 0.5 % occurred. Since the bowed wafers lead to unacceptable yield losses during the module construction, the reduction of bow is indispensable on thin crystalline silicon solar cell. In this work, we have studied on the counterbalance between the bow and conversion efficiency and also suggest the formation of enough back surface field (BSF) with thinner Al paste application.

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몰드 두께에 의한 팬 아웃 웨이퍼 레벨 패키지의 Warpage 분석 (Analysis of Warpage of Fan-out Wafer Level Package According to Molding Process Thickness)

  • 문승준;김재경;전의식
    • 반도체디스플레이기술학회지
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    • 제22권4호
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    • pp.124-130
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    • 2023
  • Recently, fan out wafer level packaging, which enables high integration, miniaturization, and low cost, is being rapidly applied in the semiconductor industry. In particular, FOWLP is attracting attention in the mobile and Internet of Things fields, and is recognized as a core technology that will lead to technological advancements such as 5G, self-driving cars, and artificial intelligence in the future. However, as chip density and package size within the package increase, FOWLP warpage is emerging as a major problem. These problems have a direct impact on the reliability and electrical performance of semiconductor products, and in particular, cause defects such as vacuum leakage in the manufacturing process or lack of focus in the photolithography process, so technical demands for solving them are increasing. In this paper, warpage simulation according to the thickness of FOWLP material was performed using finite element analysis. The thickness range was based on the history of similar packages, and as a factor causing warpage, the curing temperature of the materials undergoing the curing process was applied and the difference in deformation due to the difference in thermal expansion coefficient between materials was used. At this time, the stacking order was reflected to reproduce warpage behavior similar to reality. After performing finite element analysis, the influence of each variable on causing warpage was defined, and based on this, it was confirmed that warpage was controlled as intended through design modifications.

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A Simulated Study of Silicon Solar Cell Power Output as a Function of Minority-Carrier Recombination Lifetime and Substrate Thickness

  • Choe, Kwang Su
    • 한국재료학회지
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    • 제25권9호
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    • pp.487-491
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    • 2015
  • In photovoltaic power generation where minority carrier generation via light absorption is competing against minority carrier recombination, the substrate thickness and material quality are interdependent, and appropriate combination of the two variables is important in obtaining the maximum output power generation. Medici, a two-dimensional semiconductor device simulation tool, is used to investigate the interdependency in relation to the maximum power output in front-lit Si solar cells. Qualitatively, the results indicate that a high quality substrate must be thick and that a low quality substrate must be thin in order to achieve the maximum power generation in the respective materials. The dividing point is $70{\mu}m/5{\times}10^{-6}sec$. That is, for materials with a minority carrier recombination lifetime longer than $5{\times}10^{-6}sec$, the substrate must be thicker than $70{\mu}m$, while for materials with a lifetime shorter than $5{\times}10^{-6}sec$, the substrate must be thinner than $70{\mu}m$. In substrate fabrication, the thinner the wafer, the lower the cost of material, but the higher the cost of wafer fabrication. Thus, the optimum thickness/lifetime combinations are defined in this study along with the substrate cost considerations as part of the factors to be considered in material selection.

Thickness Dependent Temperature Accelerated Dielectric Break-down Strength of On-wafer Low Dielectric Constant Polymer Films

  • Kim, H. K.;Lee, S. W.;F. G. Shi;B. Zhao
    • KIEE International Transactions on Electrophysics and Applications
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    • 제2C권6호
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    • pp.281-286
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    • 2002
  • The temperature accelerated dielectric breakdown strength of on-wafer low-k dielectric polymer films with thicknesses ranging from 94 nm to 1141 nm is investigated by using the current-voltage characteristic measurements with MIS structures. The temperature dependence of dielectric strength is demonstrated to be Arrhenious for all thicknesses. However, the activation energy is found to be strongly thickness dependent. It follows an exponential relationship rather than being a single value, i.e., the activation energy increase significantly as film thickness increases for the thickness below 500 nm, but it is almost constant for the thickness above 500 nm. This relationship suggests that the change of the activation energy corresponding to different film thickness is closely related to the temperature dependence of the electron trapping/detrapping process in polymer thin films, and is determined by both the trapping rate and the detrapping rate. Thinner films need less energy to form a conduction path compared to thicker films. Hence, it leads to smaller activation energy in thinner films, and the activation energy increases with the increase in film thickness. However, a nearly constant value of the activation energy is achieved above a certain range of film thickness, indicating that the trapping rate and detrapping rate is almost equal and eventually the activation energy approaches the value of bulk material.

세라믹소재를 이용한 해수압센서 제작 및 전기적 특성 연구 (A Study on the Fabrication and Electrical Characteristics of Hydraulic Pressure Sensors by Using Ceramics Materials)

  • 박성현;김은섭;정정균
    • 한국전기전자재료학회논문지
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    • 제28권6호
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    • pp.384-389
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    • 2015
  • In this paper, we fabricated ceramic body and sapphire wafer in order to develop a hydraulic pressure sensor with high sensitivity and high temperature stability. The sapphire wafer was adopted with a membrane of capacitance ceramic pressure sensor. The capacitance value of the sensor for the finite element analysis(FEM) showed a linear pressure characteristics. Membrane was processed with a diameter of 32.4 mm and a thickness of 1 mm by using alumina powders. Ceramic body was processed with a diameter 32.4 mm and a thickness 5 mm. The capacitance pressure sensor was made with high heat treatment of the ceramic body and the sapphire wafer. Initially capacitance of the pressure sensor was 50 pF and a capacitance of 110 pF was measured from 5 bar pressure. Output voltage of 5 V was appeared at 5 bar pressure.

램프 가열 방식 LPCVD 장비의 설계 및 제작 (Design and Implementation of Lamp-Heated LPCVD System)

  • 하용민;김태성;김충기
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1991년도 추계학술대회 논문집 학회본부
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    • pp.299-303
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    • 1991
  • A lamp heated LPCVD equipment has been made. Wafer is heated by an array of fifteen tungsten halogen lamps above the front side of a wafer and pyrometer views the back side of the wafer through $CaF_2$ window. Reactor which consisits of a quartz window and a water cooled-stainless steel plate can be evacuated to $5{\times}10^{-3}$ torr with a rotary vane pump. By pyrolysis of $SiH_4$ at about $600^{\circ}C$, polysilicon has been formed on the silicon dioxide film. The measured results show that thickness nonuniformity is 15% and temperature nonuniformity is 1.1%. Because activation energy of pyrolysis of $SiH_4$ is very high, about 1.8eV, small temperature variation will induce large thickness nonuniformity. The main cause of temperature nonuniformity is unsymmetry of lamp power and an unbalanced cooling structure. Charls & Evans' SIMS result shows that the oxygen content in the deposited polysilicon is comparable to that of silicon substrate but carbon content is ten times higher.

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