• Journal of the Korean Society for Precision Engineering
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• v.29 no.3
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• pp.289-294
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• 2012

There are several indicators to represent characteristics of chemical mechanical planarization (CMP) such as material removal rate (MRR), surface quality and removal uniformity on a wafer surface. Especially, the removal uniformity on the wafer edge is one of the most important issues since it gives a significant impact on the yield of chip production on a wafer. Non-uniform removal rate at the wafer edge (edge effect) is mainly induced by a non-uniform pressure from nonuniform pad curvature during CMP process, resulting in edge exclusion which means the region that cannot be made to a chip. For this reason, authors tried to minimize the edge exclusion by using an edge profile control (EPC) ring. The EPC ring is equipped on the polishing head with the wafer to protect a wafer from the edge effect. Experimental results showed that the EPC ring could dramatically minimize the edge exclusion of the wafer. This study shows a possibility to improve the yield of chip production without special design changes of the CMP equipment.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.319-319
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• 2012

현재 폭넓게 이용되고 있는 STI (Shallow Trench Isolation) 공정에서 active edge 부분에 발생하는 기생 transistor의 subthreshold hump 특성을 제어하는 연구가 활발히 이루어지고 있다. 일반적으로 STI 공정을 이용하는 MOSFET에서 active edge 부분의 얇게 형성된 gate oxide, sharp한 active edge 형성, STI gap-fill 공정 중에 생기는 channel dopant out-diffusion은 subthreshold hump 특성의 주된 요인이다. 이와 같은 문제점을 해결하기 위해 active edge rounding process와 channel dopant compensation의 implantation을 이용하여 subthresold hump 특성 개선을 연구하였다. 본 연구는 STI 공정에 필요한 wafer와 phosphorus를 함유한 wafer를 한 chamber 안에서 auto-doping하는 방법을 이용하여 subthresold hump 특성을 구현하였다. phosphorus를 함유한 wafer에서 빠져나온 phosphorus가 STI 공정중인 wafer로 침투하여, active edge 부분의 channel dopant인 boron 농도를 상대적으로 낮춰 active edge 부분의 가 감소하고 leakage current를 증가시킨다. transistor의 channel length, gate width이고, wafer#No가 클수록 phosphorous를 함유한 wafer까지의 거리는 가까워진다. wafer #01은 hump 특성이 없고, wafer#20은 에서 심한 subthreshold hump 특성을 보였다. channel length 고정, gate width를 ~으로 가변하여 width에 따른 영향을 실험하였다. active 부분에 대한 SCM image로 확인된 phosphorus에 의한 active edge 부분의 boron 농도 감소와 gate width vs curve에서 확인된 phosphorus에 의한 감소가 narrow width로 갈수록 커짐을 확인하였다.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.6
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• pp.148-155
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• 2008

This study presents a process control of the wafer edge exposure (WEE) used in 300[mm] wafer environment. WEE, as a key module of the overall track system (coater and developer) for making patterns on wafer, is a system to expose the UV-ray on the wafer to remove a photo resist around edge of the wafer. It can measure, memorize and control the distance and angles from wafer center to edge. Recently in the 300[mm] semiconductor fabrication, the track system strongly requires that WEE station has a controller with high throughput and accuracy to increase process efficiency. We have designed and developed the controller, and present here a WEE control algorithm and experimental results.

• Journal of Institute of Control, Robotics and Systems
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• v.8 no.9
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• pp.812-817
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• 2002

This paper presents a development of high accuracy aligner and describes a method to find the orientation of a substantially circular disk shaped wafer with at least one flat region on an edge thereof. In the developed system, the wafer is spun one 360 degree turn on a chuck and the edge position is measured by a linear array to obtain a set of data points at various wafer orientation. The rotation axis may differ from wafer center by an unknown eccentricity. The flat angle is found by fitting a cosine curve to the actual data to obtain a deviation. The maximum deviation is then corrected for errors due to a finite number of data points and wafer eccentricity by calculating an adjustment angle from data points on the wafer fiat. After determining the flat angle the wafer is spun to the desired orientation. The wafer eccentricity can be calculated from four of the data points located away from the flat edge region. and the wafer is then centered.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.55-60
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• 2020

The hard mask photo-resist strip inspection system for the semiconductor wafer manufacturing process inspects the position of the circuit pattern formed on the wafer by measuring the distance from the edge of the wafer to the strip processing area. After that, it is an inspection system that enables you to check the process status in real time. Process defects can be significantly reduced by applying a tester that has not been applied to the existing wafer strip process, edge etching process, and wafer ashing process. In addition, it is a technology for localizing semiconductor process inspection equipment that can analyze the outer diameter of the wafer and the state of pattern formation, which can secure process stability and improve wafer edge yield.

• Journal of the Optical Society of Korea
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• v.11 no.4
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• pp.173-176
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• 2007

We present a very simple and efficient bare-wafer inspection method using a knife-edge test. The wafer front surface and inner structures are inspected simultaneously. The wafer front surface is inspected visually using a knife-edge test while the inner structure is simultaneously inspected by a camera in the infrared region with a single white-light source. This paper presents a laboratory implementation of the test method with some experimental results.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.55.4-55
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• 2002

In the semiconductor fabrication, particle contamination is wide-spread and one of major causes to yield loss. Extensive testing has revealed that even careful handling of wafers during processing may cause photo-resist materials to flake off wafer edges. So, to remove the photo-resist at the outer 5mm of wafers, UV(Ultraviolet) rays are exposed. WEE (Wafer Edge Exposure) process station is the system that exposes the wafer edge as prespecified by controlling the positioning mechanism and maintaining the light intensity level In this work, WEE process station has been designed so as to significantly lower the amount of particle contamination which occurs even during the most r...

• Journal of the Semiconductor & Display Technology
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• v.15 no.1
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• pp.56-64
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• 2016

It is generally accepted that the surface quality of wafer edge is mostly damaged by the vibrations of the edge grinding machine. The surface quality of wafer edge is supposed to be the most dominant factor of the cracks, scratches, burrs and chips on the edge surfaces, which are the main defects of the wafers. In this study, the structure of a wafer edge grinder has been investigated through the frequency response experiment and the computer simulation to find ways to suppress the vibrations from the structure. The main reasons of the structural vibrations were analyzed. And further the design alterations were deduced from the results of the experiment and the simulation, and applied to the machine to check the effects of those alterations and to eventually improve the structural stability. The result shows that the machine can have much improved stability with relatively simple design changes.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2011.06a
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• pp.183-184
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• 2011

• Tribology and Lubricants
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• v.28 no.6
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• pp.272-277
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• 2012

Finite element analysis was carried out using wafer-scale and particle-scale models to understand the mechanism of the fast removal rate(edge effect) at wafer edges in the chemical-mechanical polishing process. This is the first to report that a particle-scale model can explain the edge effect well in terms of stress distribution and magnitude. The results also revealed that the mechanism could not be fully understood by using the wafer-scale model, which has been used in many previous studies. The wafer-scale model neither gives the stress magnitude that is sufficient to remove material nor indicates the coincidence between the stress distribution and the removal rate along a wafer surface.