• 제목/요약/키워드: Wafer Shape

검색결과 135건 처리시간 0.027초

A Low- Viscousity, Highly Thermally Conductive Epoxy Molding Compound (EMC)

  • Bae, Jong-Woo;Kim, Won-Ho;Hwang, Seung-Chul;Choe, Young-Sun;Lee, Sang-Hyun
    • Macromolecular Research
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    • 제12권1호
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    • pp.78-84
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    • 2004
  • Advanced epoxy molding compounds (EMCs) should be considered to alleviate the thermal stress problems caused by low thermal conductivity and high elastic modulus of an EMC and by the mismatch of the coefficient of thermal expansion (CTE) between an EMC and the Si-wafer. Though A1N has some advantages, such as high thermal conductivity and mechanical strength, an A1N-filled EMC could not be applied to commercial products because of its low fluidity and high modules. To solve this problem, we used 2-$\mu\textrm{m}$ fused silica, which has low porosity and spherical shape, as a small size filler in the binary mixture of fillers. When the composition of the silica in the binary filler system reached 0.3, the fluidity of EMC was improved more than twofold and the mechanical strength was improved 1.5 times, relative to the 23-$\mu\textrm{m}$ A1N-filled EMC. In addition, the values of the elastic modules and the dielectric constant were reduced to 90%, although the thermal conductivity of EMC was reduced from 4.3 to 2.5 W/m-K, when compared with the 23-$\mu\textrm{m}$ A1N-filled EMC. Thus, the A1N/silica (7/3)-filled EMC effectively meets the requirements of an advanced electronic packaging material for commercial products, such as high thermal conductivity (more than 2 W/m-K), high fluidity, low elastic modules, low dielectric constant, and low CTE.

기판 Etching 기법을 이용한 DLC 필름의 탄성특성 평가 (Evaluation of Elastic Properties of DLC Films Using Substrate Etching Techniques)

  • 조성진;이광렬;은광용;한준희;고대홍
    • 한국세라믹학회지
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    • 제35권8호
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    • pp.813-818
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    • 1998
  • A simple method to measure the elastic modulus E and Poisson's ratio v of diamod-like carbon (DLC) films deposited on Si wafer was suggested. Using the anisotropic etching technique of Si we could make the edge of DLC overhang free from constraint of Si substrate. DLC film is chemically so inert that we could not on-serve any surface damage after the etching process. The edge of DLC overhang free from constraint of Si substrate exhibited periodic sinusoidal shape. By measuring the amplitude and the wavelength of the sinu-soidal edge we could determine the stain of the film required to adhere to the substrate. Since the residual stress of film can be determine independently by measurement of the curvature of film-substrate com-posite we could calculated the biaxial elastic modulus E/(1-v) using stress-strain relation of thin films. By comparing the biaxial elastic modulus with the plane-strain modulus E/(1-{{{{ { v}^{2 } }}) measured by nano-in-dentation we could further determine the elastic modulus and Poisson's ratio independently. This method was employed to measure the mechanical properties of DLC films deposited by {{{{ { {C }_{6 }H }_{6 } }} rf glow discharge. The was elastic modulus E increased from 94 to 169 GPa as the {{{{ { V}_{ b} / SQRT { P} }} increased from 127 to 221 V/{{{{ {mTorr }^{1/2 } }} Poisson's ratio was estimated to be abou 0.16∼0.22 in this {{{{ { V}_{ b} / SQRT { P} }} range. For the {{{{ { V}_{ b} / SQRT { P} }} less than 127V/{{{{ {mTorr }^{1/2 } }} where the plastic deformation can occur by the substrate etching process however the present method could not be applied.

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Utilizing Advanced Pad Conditioning and Pad Motion in WCMP

  • Kim, Sang-Yong;Chung, Hun-Sang;Park, Min-Woo;Kim, Chang-Il;Chang, Eui-Goo
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2001년도 추계학술대회 논문집
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    • pp.171-175
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    • 2001
  • Chemical mechanical polishing(CMP) process has been widely used to planarize dielectrics and metal, which can apply to employed in integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of free-defects in inter level dielectrics and metal. Especially, defects like (micro-scratch) lead to severe circuit failure, and affects yield. Current conditioning method - bladder type, orbital pad motion - usually provides unsuitable pad profile during ex-situ conditioning near the end of pad life. Since much of the pad wear occurs by the mechanism of bladder tripe conditioning and its orbital motion without rotation, we need to implement new ex-situ conditioner which can prevent abnormal regional force on pad caused by bladder-type and also need to rotate the pad during conditioning. Another important study of ADPC is related to the orbital scratch of which source is assumed as diamond grit dropped from the strip during ex-situ conditioning. Scratch from diamond grit damaged wafer severely so usual1y scraped. Figure 1 shows the typical shape of scratch damaged from diamond. We suspected that intensive forces to the edge area of bladder type stripper accelerated the drop of Diamond grit during conditioning, so new designed Flat stripper was introduced.

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메모리소자 응용을 위한 초박막의 제작 및 특성 평가 (Evaluation of the fabrications and properties of ultra-thin film for memory device application)

  • 정상현;최행철;김재현;박상진;김광호
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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    • pp.169-170
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    • 2006
  • In this study, ultra thin films of ferroelectric vinylidene fluoride-trifluoroethylene (VF2-TrFE) copolymer were fabricated on degenerated Si (n+, $0.002\;{\Omega}{\cdot}cm$) using by spin coating method. A 1~5 wt% diluted solution of purified vinylidene fluoride-trifluoroethylene (VF2:TrFE=70:30) in a dimethylformamide (DMF) solvent were prepared and deposited on silicon wafers at a spin rate of 2000~5000rpm for 30 seconds. After annealing in a vacuum ambient at $200^{\circ}C$ for 60 min, upper gold electrodes were deposited by vacuum evaporation for electrical measurement. X-ray diffraction results showed that the VF2-TrFE films on Si substrates had $\beta$-phase of copolymer structures. The capacitance on $n^+$-Si(100) wafer showed hysteresis behavior like a butterfly shape and this result indicates clearly that the dielectric films have ferroelectric properties. The typical measured remnant polarization (2Pr) and coercive filed (EC) values measured using a computer controlled a RT-66A standardized ferroelectric test system (Radiant Technologies) were about $0.54\;C/cm^2$ and 172 kV/cm, respectively, in an applied electric field of ${\pm}0.75\;MV/cm$.

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초소형 광정보저장기기용 웨이퍼 스케일 대물렌즈 제작을 위한 회절광학소자 성형기술 개발 (Fabrication of diffractive optical element for objective lens of small form factor data storage device)

  • 배형대;임지석;정기봉;한정원;유준모;박노철;강신일
    • 한국소성가공학회:학술대회논문집
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    • 한국소성가공학회 2005년도 금형가공,미세가공,플라스틱가공 공동 심포지엄
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    • pp.35-40
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    • 2005
  • The demand for small and high-capacity optical data storage devices has rapidly increased. The areal density of optical disk is increased using higher numerical aperture objective lens and shorter wavelength source. A wafer-scale stacked micro objective lens with a numerical aperture of 0.85 and a focal length of 0.467mm for the 405nm blue- violet laser was designed and fabricated. A diffractive optical element (DOE) was used to compensate the spherical aberration of the objective lens. Among the various fabrication methods for micro DOE, the UV-replication process is more suitable for mass-production. In this study, an 8-stepped DOE pattern as a master was fabricated by photolithography and reactive ion etching process. A flexible mold was fabricated for improving the releasing properties and shape accuracy in UV-molding process. In the replication process, the effects of exposing time and applied pressure on the replication quality were analyzed. Finally, the shapes of master, mold and molded pattern were measured by optical scanning profiler. The deviation between the master and the molded DOE was less than 0.1um. The efficiency of the molded DOE was measured by DOE efficiency measurement system which consists of laser source, sample holder, aperture and optical power meter, and the measured value was $84.5\%$.

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Off-Site Distortion and Color Compensation of Underwater Archaeological Images Photographed in the Very Turbid Yellow Sea

  • Jung, Young-Hwa;Kim, Gyuho;Yoo, Woo Sik
    • 보존과학회지
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    • 제38권1호
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    • pp.14-32
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    • 2022
  • Underwater photographing and image recording are essential for pre-excavation survey and during excavation in underwater archaeology. Unlike photographing on land, all underwater images suffer various quality degradations such as shape distortions, color shift, blur, low contrast, high noise levels and so on. Outcome is very often heavily photographing equipment and photographer dependent. Excavation schedule, weather conditions, and water conditions can put burdens on divers. Usable images are very limited compared to the efforts. In underwater archaeological study in very turbid water such as in the Yellow Sea (between mainland China and the Korean peninsula), underwater photographing is very challenging. In this study, off-site image distortion and color compensation techniques using an image processing/analysis software is investigated as an alternative image quality enhancement method. As sample images, photographs taken during the excavation of 800-year-old Taean Mado Shipwrecks in the Yellow Sea in 2008-2010 were mainly used. Significant enhancement in distortion and color compensation of archived images were obtained by simple post image processing using image processing/analysis software (PicMan) customized for given view ports, lenses and cameras with and without optical axis offsets. Post image processing is found to be very effective in distortion and color compensation of both recent and archived images from various photographing equipment models and configurations. Merits and demerit of in-situ, distortion and color compensated photographing with sophisticated equipment and conventional photographing equipment, which requires post image processing, are compared.

플립칩용 Sn-Cu 전해도금 솔더 범프의 형성 연구 (Formation of Sn-Cu Solder Bump by Electroplating for Flip Chip)

  • 정석원;강경인;정재필;주운홍
    • 마이크로전자및패키징학회지
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    • 제10권4호
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    • pp.39-46
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    • 2003
  • 플립칩용으로 Sn-Cu 공정 솔더 범프를 전해도금을 이용하여 제조하고 특성을 연구하였다. Si 웨이퍼 위에 UBM(Under Bump Metallization)으로 Al(400 nm)/Cu(300 nm)/Ni(400 nm)/Au(20 nm)를 전자빔 증착기로 증착하였다. 전류밀도가 1 A/d$\m^2$에서 8 A/d$\m^2$으로 증가함에 따라 Sn-Cu 솔더의 도금속도는 0.25 $\mu\textrm{m}$/min에서 2.7 $\mu\textrm{m}$/min으로 증가하였다. 이 전류밀도의 범위에서 전해도금된 Sn-Cu 도금 합금의 조성은 Sn-0.9∼1.4 wt%Cu의 거의 일정한 상태를 유지하였다. 도금 전류밀도 5 A/d$\m^2$, 도금시간 2hrs, 온도 $20^{\circ}C$의 조건에서 도금하였을 때, 기둥 직경 약 120 $\mu\textrm{m}$인 양호한 버섯 형태의 Sn-Cu 범프를 형성할 수 있었다. 버섯형 도금 범프를 $260^{\circ}C$에서 리플로우 했을 때 직경 약 140 $\mu\textrm{m}$의 구형 범프가 형성되었다. 화학성분의 균일성을 분석한 결과 버섯형 범프에서 존재하던 범프내 Sn 등 성분 원소의 불균일성은 구형 범프에서는 상당 부분 해소 되었다.

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Metal CMP 용 컨디셔너 디스크 표면에 존재하는 다이아몬드의 형상이 미치는 패드 회복력 변화 (The Pad Recovery as a function of Diamond Shape on Diamond Disk for Metal CMP)

  • 김규채;강영재;유영삼;박진구;원영만;오광호
    • 마이크로전자및패키징학회지
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    • 제13권3호
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    • pp.47-51
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    • 2006
  • 디바이스의 고집적화로 인한 다층 배선구조로 인해 초점심도가 중요해짐에 따라 표면의 평탄도가 디바이스에 매우 큰 영향을 주게 되어, 표면의 평탄도를 결정지어주는 CMP(Chemical Mechanical Polishing) 공정이 매우 중요한 요소가 되었다. CMP 공정에는 슬러리, 연마패드, 컨디셔닝 디스크와 같은 소모품들이 사용된다. 이러한 소모품 중 하나인 컨디셔닝 디스크를 이용한 컨디셔닝 공정은 CMP 공정이 끝난 후 패드의 기공과 groove 내에 잔류 하는 화학반응물이나 슬러리와 같은 잔유물들을 컨디셔닝 디스크 표면에 부착되어 있는 다이아몬드를 이용하여 제거 함으로써 연마율을 높이고, 연마 패드의 수명을 증가 시켜주는 역할을 한다. 컨디셔닝 공정을 실시함으로써 연마 패드의 수명이 연장되기 때문에 경제적인 부분에서도 큰 이점을 가지게 된다. 본 연구에서는 이러한 CMP 공정에서 중요한 역할을 하는 소모품 중 하나인 컨디셔닝 디스크 표면에 존재하는 다이아몬드의 밀도, 형상 그리고 크기에 따라 연마 패드의 회복력 변화를 알아봄으로써 효율적인 컨디션닝 디스크의 특성을 평가해 보았다.

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실리콘 실험실에 구리 오염을 방지 할 수 있는 고밀도/고균일의 Solder Bump 형성방법 (Fabrication Method of High-density and High-uniformity Solder Bump without Copper Cross-contamination in Si-LSI Laboratory)

  • 김성진;주철원;박성수;백규하;이희태;송민규
    • 마이크로전자및패키징학회지
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    • 제7권4호
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    • pp.23-29
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    • 2000
  • 사용되는 metal구분 없이 반도체 공정장비들을 사용함으로써 cross-contamination을 유발시킬 수 있다. 특히, copper(Cu)는 확산이 쉽게 되어 cross-contamination에 의해 수 ppm정도가 wafer에 오염되더라도 트랜지스터의 leakage current발생 요인으로 작용할 수 있기 때문에 Si-IC성능에 치명적인 영향을 미칠 수 있는데, Si-LSI 실험실에서 할 수 있는 공정과 Si-LSI 실험실을 나와 할 수 있는 공정으로 구분하여 최대한 Si-LSI 장비를 공유함으로써 최소한의 장비로 Cu cross-contamination문제를 해결할 수 있다. 즉, 전기도금을 할 때 전극으로 사용되어지는 TiW/Al sputtering, photoresist (PR) coating, solder bump형성을 위한 via형성까지는 Si-LSI 실험실에서 하고, 독립적인 다른 실험실에서 Cu-seed sputtering, solder 전기도금, 전극 etching, reflow공정을 하면 된다. 두꺼운 PR을 얻기 위하여 PR을 수회 도포(multiple coaling) 하고, 유기산 주석과 유기산 연의 비를 정확히 액 조성함으로서 Sn:Pb의 조성비가 6 : 4인 solder bump를 얻을 수 있었다. solder를 도금하기 전에 저속 도금으로 Cu를 도금하여, PR 표면의 Cu/Ti seed층을 via와 PR표면과의 저항 차를 이용하여 PR표면의 Cu-seed를 Cu도금 중에 etching 시킬 수 있다. 이러한 현상을 이용하여 선택적으로 via만 Cu를 도금하고 Ti층을 etching한 후, solder를 도금함으로써 저 비용으로 folder bump 높이가 60 $\mu\textrm{m}$ 이상 높고, 고 균일/고 밀도의 solder bump를 형성시킬 수 있었다.

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마이크로 칩 전기영동에 응용하기 위한 다결정 실리콘 층이 형성된 마이크로 채널의 MEMS 가공 제작 (MEMS Fabrication of Microchannel with Poly-Si Layer for Application to Microchip Electrophoresis)

  • 김태하;김다영;전명석;이상순
    • Korean Chemical Engineering Research
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    • 제44권5호
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    • pp.513-519
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    • 2006
  • 본 연구에서는 유리(glass)와 석영(quartz)을 재질로 사용하여 MEMS(micro-electro mechanical systems) 공정을 통해 전기영동(electrophoresis)을 위한 microchip을 제작하였다. UV 광이 실리콘(silicon)을 투과하지 못하는 점에 착안하여, 다결정 실리콘(polycrystalline Si, poly-Si) 층을 채널 이외의 부분에 증착시킨 광 차단판(optical slit)에 의해 채널에만 집중된 UV 광의 신호/잡음비(signal-to-noise ratio: S/N ratio)를 크게 향상시켰다. Glass chip에서는 증착된 poly-Si 층이 식각 마스크(etch mask)의 역할을 하는 동시에 접합표면을 적절히 형성하여 양극 접합(anodic bonding)을 가능케 하 였다. Quartz 웨이퍼에 비해 불순물을 많이 포함하는 glass 웨이퍼에서는 표면이 거친 채널 내부를 형성하게 되어 시료용액의 미세한 흐름에 영향을 미치게 된다. 이에 따라, HF와 $NH_4F$ 용액에 의한 혼합 식각액(etchant)을 도입하여 표면 거칠기를 감소시켰다. 두 종류의 재질로 제작된 채널의 형태와 크기를 관찰하였고, microchip electrophoresis에 적용한 결과, quartz과 glass chip의 전기삼투 흐름속도(electroosmotic flow velocity)가 0.5와 0.36 mm/s로 측정되었다. Poly-Si 층에 의한 광 차단판의 존재에 의해, peak의 S/N ratio는 quartz chip이 약 2배 수준, glass chip이 약 3배 수준으로 향상되었고, UV 최대흡광 감도는 각각 약 1.6배 및 1.7배 정도 증가하였다.