• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.55-60
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• 2020

The hard mask photo-resist strip inspection system for the semiconductor wafer manufacturing process inspects the position of the circuit pattern formed on the wafer by measuring the distance from the edge of the wafer to the strip processing area. After that, it is an inspection system that enables you to check the process status in real time. Process defects can be significantly reduced by applying a tester that has not been applied to the existing wafer strip process, edge etching process, and wafer ashing process. In addition, it is a technology for localizing semiconductor process inspection equipment that can analyze the outer diameter of the wafer and the state of pattern formation, which can secure process stability and improve wafer edge yield.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.55.4-55
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• 2002

In the semiconductor fabrication, particle contamination is wide-spread and one of major causes to yield loss. Extensive testing has revealed that even careful handling of wafers during processing may cause photo-resist materials to flake off wafer edges. So, to remove the photo-resist at the outer 5mm of wafers, UV(Ultraviolet) rays are exposed. WEE (Wafer Edge Exposure) process station is the system that exposes the wafer edge as prespecified by controlling the positioning mechanism and maintaining the light intensity level In this work, WEE process station has been designed so as to significantly lower the amount of particle contamination which occurs even during the most r...

• Proceedings of the Korea Association of Crystal Growth Conference
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• 1996.06a
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• pp.88-138
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• 1996

Electronics grew up to the largest industry in the world supported by Si wafer. In near future, the Si wafer may use 300mm in diameter for economic requirement. This size wafer may use to produce large logic chip, 256Mbit DRAM, and other large complex and high density chip. Then, the quality including flatness and crustal characters may be required very high performance. And, their price should be reasonable and high quantity may be required. These requirements should be solve lot of hard problems of crystal growth, wafering mechanical processing and their cost problems. In this presentation, I may discuss following items.

• Journal of the Semiconductor & Display Technology
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• v.19 no.2
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• pp.77-81
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• 2020

Silicon wafer etching in micro electro mechanical systems (MEMS) fabrication is challenging to form 3-D structures. Well known Si-wet etch of silicon employs potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH) and sodium hydroxide (NaOH). However, the existing silicon wet etching process has a fatal disadvantage that etching of the back side of the wafer is hard to avoid. In this study, a wet etching bath for 150 mm wafers was designed to prevent back-side etching of silicon wafer, and we demonstrated the optimized process recipe to have anisotropic wet etching of silicon wafer without any damage on the backside. We also presented the design of wet bath for 300 mm wafer processing as a promising process development.

• Proceedings of the Materials Research Society of Korea Conference
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• 2002.11a
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• pp.48-48
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• 2002

• Transactions of the Korean Society of Mechanical Engineers
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• v.16 no.4
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• pp.609-620
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• 1992

A numerical solution of temperature and thermally induced stress in a wafer during rapid thermal processing (R.T.P) is obtained, and an analysis of onset and propagation of slip is performed and compared with experiment. In order to calculate temperature distribution of a wafer in R.T.P system, heat conduction equation that incorporated with radiative and convective heat transfer model is solved, and the solution of the equation is calculated numerically using alternating direction implicit (A.D.I) method. In dealing with radiative heat transfer, a partially transparent body that absorbs the radiation energy is assumed and this transparent body undergoes multiple internal reflections and absorptions. Two dimensional (assuming plane stress) thermoelastic constitutive equation is used to calculate thermal stress induced in a wafer and finite element method is employed to solve the equation numerically. The stress resolved in the slip directions on the slip planes of silicon is compared with the yield stress of silicon in order to predict the slip. The result of the analysis shows that the wafer temperature at which slip occurs is affected by the heating rate of the R.T.P system. It is observed that once slip occurs in the wafer, the slip grows.

• Journal of Advanced Navigation Technology
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• v.13 no.3
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• pp.412-418
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• 2009

This study aims to develop a system that enables 20 to 25 wafers to be automatically aligned at the position of the corresponding serial number and facilitates the checkout of wafer processing by sensing them before and after semiconductor processing. It also suggests compensation algorithm and stepper motor control algorithm that carefully align notches. This study minimizes the rate of occurrence by adopting materials of which the surface has proper coefficient of friction when wafers are rotating and that do not rarely produce particles. This study completed the development of a slip resistance apparatus and carried out performance tests through mathematical verification. This system is expected to improve semiconductor yield due to anti-pollution technology in semiconductor processing and can be selectively applied to a large size wafer over 450mm in the future.

• Proceedings of the Korean Society of Laser Processing Conference
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• 2006.11a
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• pp.128-132
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• 2006

Low-k wafer engraving process has been investigated by using UV pico-second laser with high repetition rate. Wavelength and repetition rate of laser used in this study are 355nm and 80MHz, respectively. Main parameters of low-k wafer engraving processes are laser power, work speed, assist gas flow rate, and protective coating to eliminate debris. Results show that engraving qualities of low-k layer by using UV pico-second pulse width and high repetition rate had better kerf edge and higher work speed, compared to one by conventional laser with nano-second pulse width and low repetition rate in the range of kHz. Assist gas and protective coating to eliminate debris gave effects on the quality of engraving edge. Total engraving width and depth are obtained less than $20{\mu}m$ and $10{\mu}m$ at more than 500mm/sec work speed, respectively. We believe that engraving method by using UV pico-second laser with high repetition rate is useful one to give high work speed of laser material process.

• Korean Journal of Materials Research
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• v.15 no.9
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• pp.613-619
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• 2005

The ever increasing popularity and acceptance in the market place of portable systems, such as cell phones, PDA, notebook PC, etc., are fueling effects in further miniaturizing and lowering power consumption in these systems. The dynamic power consumption due to the CPU activities and the static power consumption due to leakage currents are two major sources of power consumption. Smaller devices and a lower de voltage lead to reducing the power requirement, while better insulation and isolation of devices lead to reducing leakage currents. All these can be harnessed in the SOI (silicon-on-insulator) technology. In this study, the key aspects of the SOI technology, mainly device electrical properties and device processing steps, are briefly reviewed. The interesting materials issues, such as SOI structure formation and SOI wafer fabrication methods, are then surveyed. In particular, the recent technological innovations in two major SOI wafer fabrication methods, namely wafer bonding and SIMOX, are explored and compared in depth. The results of the study are nixed in that, although the quality of the SOI structures has shown great improvements, the processing steps are still found to be too complex. Between the two methods, no clear winner has yet emerged in terms of the product quality and cost considerations.

• Laser Solutions
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• v.6 no.3
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• pp.29-35
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• 2003

In semiconductor processing, there are two types of particle contaminated onto the wafer, i.e. dry and wet state particles. In order to evaluate the cleaning performance of laser shock wave cleaning method, the removal of 1 m sized alumina particle at different particle conditions from silicon wafer has been carried out by laser-induced shock waves. It was found that the removal efficiency by laser shock cleaning was strongly dependent on the particle condition, i.e. the removal efficiency of dry alumina particle from silicon wafer was around 97％ while the efficiencies of wet alumina particle in DI water and IPA are 35％ and 55％ respectively. From the analysis of adhesion forces between the particle and the silicon substrate, the adhesion force of the wet particle where capillary force is dominant is much larger than that of the dry particle where Van der Waals force is dominant. As a result, it is seen that the particle in wet condition is much more difficult to remove from silicon wafer than the particle in dry condition by using physical cleaning method such as laser shock cleaning.