• 제목/요약/키워드: Wafer Processing

검색결과 232건 처리시간 0.025초

다이아몬드 형상에 따른 컨디셔너 디스크의 특성 평가 (The Characterization of the Conditioner Disks with Various Diamond Shapes)

  • 김규채;강영재;유영삼;박진구;원영만;오광호
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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    • pp.563-564
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    • 2006
  • Recently, CMP (Chemical Mechanical Polishing) is one of very important processing in semiconductor technology because of large integration and application of design role. CMP is a planarization process of wafer surface using the chemical and mechanical reactions. One of the most important components of the CMP system is the polishing pad. During the CMP process, the pad itself becomes smoother and glazing. Therefore it is necessary to have a pad conditioning process to refresh the pad surface, to remove slurry debris and to supply the fresh slurry on the surface. A diamond disk use during the pad conditioning. There are diamonds on the surface of diamond disk to remove slurry debris and to polish pad surface slightly, so density, shape and size of diamond are very important factors. In. this study, we characterized diamond disk with 9 kinds of sample.

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양팔 클러스터장비의 초기 전이 기간 스케줄링 (Scheduling Start-up Transient Periods of Dual Armed Cluster Tools)

  • 홍경효;김자희
    • 한국시뮬레이션학회논문지
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    • 제24권3호
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    • pp.17-26
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    • 2015
  • 생산성과 웨이퍼의 품질을 향상하기 위해 다양한 공정에서 사용되는 클러스터 장비는 단순한 구성에도 불구하고 병렬 공정모듈, 중간버퍼의 부재, 시간 제약 때문에 스케줄이 쉽지 않다. 그래서 스케줄링에 대한 많은 연구가 진행되었지만 대부분 시간이 변동되지 않는다는 가정 하에서 주기별로 동일한 스케줄이 반복되는 안정 상태를 연구하였다. 본 연구에서는 시간 제약을 만족시키면서도 원하는 안정 상태의 스케줄로 안착할 수 있는 스케줄 전략을 제시한다. 제안된 스케줄 전략은 작업시간이 지속적으로 변동되는 상황에서도 강건하다. 마지막으로 이 전략들이 실제로 강건하고, 원하는 안정 상태로 갈 수 있다는 것을 보여주기 위하여 시뮬레이션을 수행한다.

Digital Image Comparisons for Investigating Aging Effects and Artificial Modifications Using Image Analysis Software

  • Yoo, Yeongsik;Yoo, Woo Sik
    • 보존과학회지
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    • 제37권1호
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    • pp.1-12
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    • 2021
  • In the digital era, large archives of information and Internet accessibility make information search, including image search, easier and affordable, even from remote locations. Information transmission and sharing can be performed instantly, at any moment. In the case of images, there are risks of transmitting and recklessly sharing intentionally modified images. Such modified images can also be transmitted and used as an additional source of information by followers. In this study, historical portraits of Yu Kil-Chun are shown, who was the first Korean student to study in both Japan and the United States. He was an intellectual, writer, politician, and independence activist of Korea's late Joseon Dynasty. Using image processing software, the portrait images were compared to investigate aging effects and artificial modifications. Statistics of red (R), green (G), blue (B), and L*, a*, and b* values of every pixel in the selected identical areas of the portraits were compared to identify possible causes of variations, including aging effects and artificial modifications. Sepia toning, used in black and white photographs until the 1930s, and modern digital sepia toning can be very confusing owing to their aging effects. The importance of preservation of physical copies and preservation of context (interconnections between data and between documents) is discussed from archiving and conservation science perspectives.

인공신경망을 활용한 CMP 컨디셔닝 시스템 설계 변수에 따른 컨디셔닝 밀도의 불균일도 분석 (Nonuniformity of Conditioning Density According to CMP Conditioning System Design Variables Using Artificial Neural Network)

  • 박병훈;이현섭
    • Tribology and Lubricants
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    • 제38권4호
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    • pp.152-161
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    • 2022
  • Chemical mechanical planarization (CMP) is a technology that planarizes the surfaces of semiconductor devices using chemical reaction and mechanical material removal, and it is an essential process in manufacturing highly integrated semiconductors. In the CMP process, a conditioning process using a diamond conditioner is applied to remove by-products generated during processing and ensure the surface roughness of the CMP pad. In previous studies, prediction of pad wear by CMP conditioning has depended on numerical analysis studies based on mathematical simulation. In this study, using an artificial neural network, the ratio of conditioner coverage to the distance between centers in the conditioning system is input, and the average conditioning density, standard deviation, nonuniformity (NU), and conditioning density distribution are trained as targets. The result of training seems to predict the target data well, although the average conditioning density, standard deviation, and NU in the contact area of wafer and pad and all areas of the pad have some errors. In addition, in the case of NU, the prediction calculated from the training results of the average conditioning density and standard deviation can reduce the error of training compared with the results predicted through training. The results of training on the conditioning density profile generally follow the target data well, confirming that the shape of the conditioning density profile can be predicted.

BUMPLESS FLIP CHIP PACKAGE FOR COST/PERFORMANCE DRIVEN DEVICES

  • Lin, Charles W.C.;Chiang, Sam C.L.;Yang, T.K.Andrew
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2002년도 International Symposium
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    • pp.219-225
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    • 2002
  • This paper presents a novel "bumpless flip chip package"for cost! performance driven devices. Using the conventional electroplating and etching processes, this package enables the production of fine pitch BGA up to 256 I/O with single layer routing. An array of circuitry down to $25-50{\mu}{\textrm}{m}$ line/space is fabricated to fan-in and fan-out of the bond pads without using bumps or substrate. Various types of joint methods can be applied to connect the fine trace and the bond pad directly. The resin-filled terminal provides excellent compliancy between package and the assembled board. More interestingly, the thin film routing is similar to wafer level packaging whereas the fan-out feature enables high lead count devices to be accommodated in the BGA format. Details of the design concepts and processing technology for this novel package are discussed. Trade offs to meet various cost or performance goals for selected applications are suggested. Finally, the importance of design integration early in the technology development cycle with die-level and system-level design teams is highlighted as critical to an optimal design for performance and cost.

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Plasma etching behavior of RE-Si-Al-O glass (RE: Y, La, Gd)

  • 이정기;황성진;이성민;김형순
    • 한국재료학회:학술대회논문집
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    • 한국재료학회 2010년도 춘계학술발표대회
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    • pp.49.1-49.1
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    • 2010
  • The particle generation during the plasma enhanced process is highly considered as serious problem in the semiconductor manufacturing industry. The material for the plasma processing chamber requires the plasma etching characteristics which are homogeneously etched surface and low plasma etching depth for preventing particulate contamination and high durability. We found that the materials without grain boundaries can prevent the particle generation. Therefore, the amorphous material with the low plasma etching rate may be the best candidate for the plasma processing chamber instead of the polycrystalline materials such as yttria and alumina. Three glasses based on $SiO_2$ and $Al_2O_3$ were prepared with various rare-earth elements (Gd, Y and La) which are same content in the glass. The glasses were plasma etched in the same condition and their plasma etching rate was compared including reference materials such as Si-wafer, quartz, yttria and alumina. The mechanical and thermal properties of the glasses were highly related with cationic field strength (CFS) of the rare-earth elements. We assumed that the plasma etching resistance may highly contributed by the thermal properties of the fluorine byproducts generated during the plasma exposure and it is expected that the Gd containing glass may have the highest plasma etching resistance due to the highest sublimation temperature of $GdF_3$ among three rare-earth elements (Gd, Y and La). However, it is found that the plasma etching results is highly related with the mechanical property of the glasses which indicates the cationic field strength. From the result, we conclude that the glass structure should be analyzed and the plasma etching test should be conducted with different condition in the future to understand the plasma etching behavior of the glasses perfectly.

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150 mm GaAs 웨이퍼의 플라즈마 식각에서 식각 깊이의 균일도에 대한 가스 흐름의 최적화 연구 (Effect of Gas now Modulation on Etch Depth Uniformity for Plasma Etching of 150 mm GaAs Wafers)

  • 정필구;임완태;조관식;전민현;임재영;이제원;조국산
    • 한국진공학회지
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    • 제11권2호
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    • pp.113-118
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    • 2002
  • 대면적 GaAs 웨이퍼의 플라즈마 식각 공정에서 식각 깊이의 좋은 균일도를 얻기 위해 반응기 내의 가스 흐름을 조절하는 진보된 기술을 실험하였다. 유한차분수치법(Finite Difference Numerical Method)은 GaAs 웨이퍼의 건식 식각을 위한 반응기 안의 가스 흐름의 분포를 시뮬레이션하기에 유용한 방법이다. 이 방법을 이용해 시뮬레이션된 자료와 실제의 것이 상당히 일치한다는 것이 $BCl_3/N_2/SF_6/He$ICP플라즈마의 실험 결과로 확인되었다. 대면적 GaAs 웨이퍼의 플라즈마 식각 공정 중에서 포커스 링(focus ring)의 최적화된 위치가 가스 흐름과 식각 균일성을 동시에 향상시키는 것을 이해했다. 반응기와 전극(electrode)의 크기가 변하지 않는 상황에서 샘플을 고정시키는 클램프 배치의 최적화를 통해 100 mm(4 inch) GaAs 웨이퍼에서 가스 흐름의 균일성을 $\pm$1.5 %, 150 mm(6 inch) 웨이퍼에서는 $\pm$3% 이하로 유지시킬 수 있는 것을 시뮬레이션결과에서 확인할 수 있다. 시뮬레이션된 가스 흐름의 균일도 자료와 실제 식각 깊이 분포실험 데이터의 비교로 대면적 GaAs 웨이퍼에서 건식 식각의 뛰어난 균일성을 얻기 위해서는 반응기 내의 가스흐름분포의 조절이 매우 중요함을 확인하였다.

저온 및 고전류밀도 조건에서 전기도금된 구리 박막 간의 열-압착 직접 접합 (Thermal Compression of Copper-to-Copper Direct Bonding by Copper films Electrodeposited at Low Temperature and High Current Density)

  • 이채린;이진현;박기문;유봉영
    • 한국표면공학회:학술대회논문집
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    • 한국표면공학회 2018년도 춘계학술대회 논문집
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    • pp.102-102
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    • 2018
  • Electronic industry had required the finer size and the higher performance of the device. Therefore, 3-D die stacking technology such as TSV (through silicon via) and micro-bump had been used. Moreover, by the development of the 3-D die stacking technology, 3-D structure such as chip to chip (c2c) and chip to wafer (c2w) had become practicable. These technologies led to the appearance of HBM (high bandwidth memory). HBM was type of the memory, which is composed of several stacked layers of the memory chips. Each memory chips were connected by TSV and micro-bump. Thus, HBM had lower RC delay and higher performance of data processing than the conventional memory. Moreover, due to the development of the IT industry such as, AI (artificial intelligence), IOT (internet of things), and VR (virtual reality), the lower pitch size and the higher density were required to micro-electronics. Particularly, to obtain the fine pitch, some of the method such as copper pillar, nickel diffusion barrier, and tin-silver or tin-silver-copper based bump had been utillized. TCB (thermal compression bonding) and reflow process (thermal aging) were conventional method to bond between tin-silver or tin-silver-copper caps in the temperature range of 200 to 300 degrees. However, because of tin overflow which caused by higher operating temperature than melting point of Tin ($232^{\circ}C$), there would be the danger of bump bridge failure in fine-pitch bonding. Furthermore, regulating the phase of IMC (intermetallic compound) which was located between nickel diffusion barrier and bump, had a lot of problems. For example, an excess of kirkendall void which provides site of brittle fracture occurs at IMC layer after reflow process. The essential solution to reduce the difficulty of bump bonding process is copper to copper direct bonding below $300^{\circ}C$. In this study, in order to improve the problem of bump bonding process, copper to copper direct bonding was performed below $300^{\circ}C$. The driving force of bonding was the self-annealing properties of electrodeposited Cu with high defect density. The self-annealing property originated in high defect density and non-equilibrium grain boundaries at the triple junction. The electrodeposited Cu at high current density and low bath temperature was fabricated by electroplating on copper deposited silicon wafer. The copper-copper bonding experiments was conducted using thermal pressing machine. The condition of investigation such as thermal parameter and pressure parameter were varied to acquire proper bonded specimens. The bonded interface was characterized by SEM (scanning electron microscope) and OM (optical microscope). The density of grain boundary and defects were examined by TEM (transmission electron microscopy).

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전도성 페이스트 도포량 변화에 따른 결정질 태양광 모듈의 전기적 특성에 대한 영향성 분석 (Influence of the Amount of Conductive Paste on the Electrical Characteristics of c-Si Photovoltaic Module)

  • 김용성;임종록;신우균;고석환;주영철;황혜미;장효식;강기환
    • 한국재료학회지
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    • 제29권11호
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    • pp.720-726
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    • 2019
  • Recently, research on cost reduction and efficiency improvement of crystalline silicon(c-Si) photovoltaic(PV) module has been conducted. In order to reduce costs, the thickness of solar cell wafers is becoming thinner. If the thickness of the wafer is reduced, cracking of wafer may occur in high temperature processes during the c-Si PV module manufacturing process. To solve this problem, a low temperature process has been proposed. Conductive paste(CP) is used for low temperature processing; it contains Sn57.6Bi0.4Ag component and can be electrically combined with solar cells and ribbons at a melting point of $150^{\circ}C$. Use of CP in the PV module manufacturing process can minimize cracks of solar cells. When CP is applied to solar cells, the output varies with the amount of CP, and so the optimum amount of CP must be found. In this paper, in order to find the optimal CP application amount, we manufactured several c-Si PV modules with different CP amounts. The amount control of CP is fixed at air pressure (500 kPa) and nozzle diameter 22G(outer diameter 0.72Ø, inner 0.42Ø) of dispenser; only speed is controlled. The c-Si PV module output is measured to analyze the difference according to the amount of CP and analyzed by optical microscope and Alpha-step. As the result, the optimum amount of CP is 0.452 ~ 0.544 g on solar cells.

실리카 에어로겔 박막의 극저 유전특성 (Ultralow Dielectric Properties of $SiO_2$ Aerogel Thin Films)

  • 현상훈;김중정;김동준;조문호;박형호
    • 한국세라믹학회지
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    • 제34권3호
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    • pp.314-322
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    • 1997
  • 극저 유전특성을 갖는 SiO2 에어로겔의 박막화의 층간 절연막으로써의 응용성이 연구되었다. 점도가 10~14cP인 SiO2 폴리머 졸을 이소프로판을 분위기 하에서 1000~7000m으로 p-Si(111) 웨이퍼 상에 스핀코팅한 습윤겔 박막을 25$0^{\circ}C$와 1160 psing 조건에서 초임계건조하여 0.5 g/㎤ 정도의 밀도(78% 기공율) 와 4000~21000$\AA$ 범위의 두께를 갖는 SiO2 에어로겔 박막을 제조하였다. 박막의 두께와 미세구조를 제어할 수 있는 주요 인자는 졸의 농도, 회전속도 및 습윤겔 숙성시간임을 알 수 있었다. SiO2 에어로겔 박막의 유전상수 값은 giga급 이상의 차세대 반도체 소자에 충분히 응용될 수 있을 정도로 낮은 2.0 정도이었다.

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