• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1997년도 춘계학술대회 논문집
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• pp.921-926
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• 1997

SOI(Silicon On lnsulator) technology is many advantages in the gabrication of MOS(Metal-Oxide Semiconductor) and CMOS(Complementary MOS) structures. These include high speed, lower dynamic power consumption,greater packing density, increased radiation tolearence et al. In smiple form of bonded SOL wafer manufacturing, creation of a bonded SOI structure involves oxidizing at least one of the mirror polished silicon surfaces, cleaning the oxidized surface and the surface of the layer to which it will be bonded,bringing the two cleanded surfaces together in close physical proximity, allowing the subsequent room temperature bonding to proceed to completion, and than following this room temperature joining with some form of heat treatment step,and device wafer is thinned to the target thickness. This paper has been performed to investigate the possibility of the bonded SOI wafer manufacturing Especially, we focused on the bonding quality and thinning method. Finally,we achieved the bonded SOI wafer that Si layer thickness is below 3 .mu. m and average roughness is below 5.angs.

• 반도체디스플레이기술학회지
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• 제11권2호
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• pp.63-69
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• 2012

As decreasing size of chips, the need of wafer level packaging is increased in semi-conductor and display industries. Temperature uniformity is a crucial factor in vacuum soldering process to guarantee quality of bonding between chips and wafer. In this paper, a stepwise iterative algorithm has been suggested to obtain output profile of each heat source. Since this algorithm is based on open-loop stepwise iterative experimental technique, it is easier to implement and cost effective than real time feedback controls. Along with some experiments, it was shown that the suggested algorithm can remarkably improve temperature uniformity of wafer during whole heating process compared with the ordinary manual trial-and error method.

• Korean Chemical Engineering Research
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• 제45권5호
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• pp.466-472
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• 2007

웨이퍼 레벨(WL) 3차원(3D) 집적을 구현하기 위해 저유전체 고분자를 본딩 접착제로 이용한 웨이퍼 본딩과, 적층된 웨이퍼간 전기배선 형성을 위해 구리 다마신(damascene) 공정을 사용하는 방법을 소개한다. 이러한 방법을 이용하여 웨이퍼 레벨 3차원 칩의 특성 평가를 위해 적층된 웨이퍼간 3차원 비아(via) 고리 구조를 제작하고, 그 구조의 기계적, 전기적 특성을 연속적으로 연결된 서로 다른 크기의 비아를 통해 평가하였다. 또한, 웨이퍼간 적층을 위해 필수적인 저유전체 고분자 수지를 이용한 웨이퍼 본딩 공정의 다음과 같은 특성 평가를 수행하였다. (1) 광학 검사에 의한 본딩된 영역의 정도 평가, (2) 면도날(razor blade) 시험에 의한 본딩된 웨이퍼들의 정성적인 본딩 결합력 평가, (3) 4-점 굽힘시험(four point bending test)에 의한 본딩된 웨이퍼들의 정량적인 본딩 결합력 평가. 본 연구를 위해 4가지의 서로 다른 저유전체 고분자인 benzocyclobutene(BCB), Flare, methylsilsesquioxane(MSSQ) 그리고 parylene-N을 선정하여 웨이퍼 본딩용 수지에 대한 적합성을 검토하였고, 상기 평가 과정을 거쳐 BCB와 Flare를 1차적인 본딩용 수지로 선정하였다. 한편 BCB와 Flare를 비교해 본 결과, Flare를 이용하여 본딩된 웨이퍼들이 BCB를 이용하여 본딩된 웨이퍼보다 더 높은 본딩 결합력을 보여주지만, BCB를 이용해 본딩된 웨이퍼들은 여전히 칩 back-end-of-the-line (BEOL) 공정조건에 부합되는 본딩 결합력을 가지는 동시에 동공이 거의 없는 100%에 가까운 본딩 영역을 재현성있게 보여주기 때문에 본 연구에서는 BCB가 본딩용 수지로 더 적합하다고 판단하였다.

• 센서학회지
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• 제29권5호
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• pp.354-359
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• 2020

The high vacuum hermetic sealing technique ensures excellent performance of MEMS resonators. For the high vacuum hermetic sealing, the customization of anodic bonding equipment was conducted for the glass/Si/glass triple-stack anodic bonding process. Figure 1 presents the schematic of the MEMS resonator with triple-stack high-vacuum anodic bonding. The anodic bonding process for vacuum sealing was performed with the chamber pressure lower than 5 × 10^-6 mbar, the piston pressure of 5 kN, and the applied voltage was 1 kV. The process temperature during anodic bonding was 400 ℃. To maintain the vacuum condition of the glass cavity, a getter material, such as a titanium thin film, was deposited. The getter materials was active at the 400 ℃ during the anodic bonding process. To read out the electrical signals from the Si resonator, a vertical feed-through was applied by using through glass via (TGV) which is formed by sandblasting technique of cap glass wafer. The aluminum electrodes was conformally deposited on the via-hole structure of cap glass. The TGV process provides reliable electrical interconnection between Si resonator and aluminum electrodes on the cap glass without leakage or electrical disconnection through the TGV. The fabricated MEMS resonator with proposed vacuum packaging using three-layer anodic bonding process has resonance frequency and quality factor of about 16 kHz and more than 40,000, respectively.

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2004년도 동계학술연구발표회 논문개요집
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• pp.175-176
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• 2004

An integrated waveguide optical isolator by wafer direct bonding has been studied. The isolation ratio was found to be 2.9dB in our device. We found that wafer direct bonding between the InP and GGG is effective for the integration of a waveguide optical isolator.

• 한국전기전자재료학회논문지
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• 제11권10호
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• pp.815-819
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• 1998

The silicon-nirtide membrane structure for IR sensor was fabricated through the etching and the direct bonding. The PRO($PbTiO_3$ ) layer for a IR detection was coated on the membrane and its characteristics were measured. The a attack of PTO layer during the etching of silicon wafer as well as the thermal isolation of the IR detection layer were eliminated through the method of bonding/etching of silicon wafer. The surface roughness of the membrane was measured by AFM, the micro voids and the non-contacted area were inspected by the PTO layer were measured, too.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2007년도 춘계학술발표대회 및 제12회 신소재 심포지엄
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• pp.14.2-14.2
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• 2007

• 한국전기전자재료학회논문지
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• 제30권10호
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• pp.615-624
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• 2017

This study investigated the various physical and electrical effects of silicon direct bonding. Direct bonding means the joining of two wafers together without an intermediate layer. If the surfaces are flat, and made clean and smooth using HF treatment to remove the native oxide layer, they can stick together when brought into contact and form a weak bond depending on the physical forces at room temperature. An IR camera and acoustic systems were used to analyze the voids and bonding conditions in an interface layer during bonding experiments. The I-V and C-V characteristics are also reported herein. The capacitance values for a range of frequencies were measured using a LCR meter. Direct wafer bonding of silicon is a simple method to fuse two wafers together; however, it is difficult to achieve perfect bonding of the two wafers. The direct bonding technology can be used for MEMS and other applications in three-dimensional integrated circuits and special devices.

• International Journal of Advanced Culture Technology
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• 제8권2호
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• pp.246-251
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• 2020

Dimethyl Ether(DME) engine use a highly efficient alternative fuel having a great quantity of oxygen and has a advantage no polluting PM gas. The existing DME fuel cam material is a highly expensive carbide alloy, and it is difficult to take a price advantage. Therefore the study of replacing body area with inexpensive steel material excluding piston shoe and contact area which demands high characteristics is needed. The development of WC-Ni base carbide alloy optimal bonding composition technique was accomplished in this study. To check out the influence of bonding temperature and time, bonding characteristics of sintering temperature was experimented. The hardness of specimen and bonding rate were measured using ultrasound equipment. The bonding state of each condition was excellent, and the thickness of mid-layer, temperature and maintaining time were measured. The mid-layer thickness according to bonding temperature and maintaining time were observed with optical microscope. We analyzed the micro-structural analysis, formation of bonding specimen, wafer fabrication and fuel cam abrasion test. Throughout this study, we confirmed that the fuel cam for DME engine which demands high durability against velocity and pressure is excellent.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2002년도 추계학술대회 논문집
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• pp.1033-1036
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• 2002

Wafer bonding methods such as fusion and anodic bonding suffer from high temperature treatment, long processing time, and possible damage to the micro-scale sensor or actuators. In the localized bonding process, beating was conducted locally while the whole wafer is maintained at a relatively low temperature. But previous research of localized heating has some problems, such as non-uniform soldering due to non-uniform heating and micro crack formation on the glass capsule by thermal stress effect. To address this non-uniformity problem, a new heater configuration is being proposed. By keeping several points on the heater strip at calculated and constant potential, more uniform heating, hence more reliable wafer bonding could be achieved. The proposed scheme has been successfully demonstrated, and the result shows that it will be very useful in hermetic packaging. Less than 0.2 ㎫ contact Pressure were used for bonding with 150 ㎃ current input for 50${\mu}{\textrm}{m}$ width, 2${\mu}{\textrm}{m}$ height and 8mm $\times$ 8mm, 5mm$\times$5mm, 3mm $\times$ 3mm sized phosphorus-doped poly-silicon micro heater. The temperature can be raised at the bonding region to 80$0^{\circ}C$, and it was enough to achieve a strong and reliable bonding in 3minutes. The IR camera test results show improved uniformity in heat distribution compared with conventional micro heaters. For gross leak check, IPA (Isopropanol Alcohol) was used. Since IPA has better wetability than water, it can easily penetrate small openings, and is more suitable for gross leak check. The pass ratio of bonded dies was 70%, for conventional localized heating, and 85% for newly developed FP scheme. The bonding strength was more than 30㎫ for FP scheme packaging, which shows that FP scheme can be a good candidate for micro scale hermetic packaging.