• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.98-101
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• 2003

As the ultra precision grinding can be applied to wafering process by the refinement of the abrasive. the development of high stiffness equipment and grinding skill, the conventional wafering process which consists of lapping, etching, 1st, 2nd and 3rd polishing could be exchanged to the new process which consists of precision surface grinding, final polishing and post cleaning. Especially, the ultra precision grinding of wafer improves the flatness of wafer and the efficiency of production. Futhermore, it has been not only used in bare wafer grinding, but also applied to wafer back grinding and SOI wafer grinding. This paper focused on the flatness of the ground wafer. Generally, the ground wafer has concave profile because of the difference of wheel path density, grinding temperature and elastic deformation of the equiptment. Tilting mathod is applied to avoid such non-uniform material removes. So, in this paper, the geometric analysis on grinding process is carried out, and then, we can predict the profile of th ground wafer by using profile simulation.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.12
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• pp.2217-2220
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• 2007

In this paper, we propose a new wafer level package (WLP) for the RF MEMS applications. The Film Bulk Acoustic Resonator (FBAR) are fabricated and hermetically packaged in a new wafer level packaging process. With the use of Au-Sn eutectic bonding method, we bonded glass cap and FBAR device wafer which has groove-shaped via formed in the backside. The device wafer includes a electrical bonding pad and groove-shaped via for connecting to the external bonding pad on the device wafer backside and a peripheral pad placed around the perimeter of the device for bonding the glass wafer and device wafer. The glass cap prevents the device from being exposed and ensures excellent mechanical and environmental protection. The frequency characteristics show that the change of bandwidth and frequency shift before and after bonding is less than 0.5 MHz. Two packaged devices, Tx and Rx filters, are attached to a printed circuit board, wire bonded, and encapsulated in plastic to form the duplexer. We have designed and built a low-cost, high performance, duplexer based on the FBARs and presented the results of performance and reliability test.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.10a
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• pp.484-487
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• 1997

The dicing is a process of gaining chip from a wafer. It is done by some mechanism to lengthwise and crosswise. Here, it is focused on measuring a depth of the wafer hefore a process of the dicing. First of all, it checks a precise outer position for the wafer on table to gain the chip. Second, the xafer should he lined after Imowing how much depth, it is in out of the outer position of the wafer. Here suggests that there are a composition of mechanical system, how to measure a depth out of scriber axis, a result from testing.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2003.05a
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• pp.74-79
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• 2003

This paper is concerned with the estimation of a wafer part in grasping system. The estimation of a wafer size in grasping system is very important because a wafer must be placed in accurate position. The accurate information of a wafer size should be forward to Robot in order to place a wafer in accurate position. So in this paper, we decide the size of a wafer with Fuzzy Logic and consider the possibility of this method by simulation.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.203.1-203.1
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• 2016

Poly etch 설비에서 발생하는 dechuck 불량에 의한 Dynamic Alignment(DA) error는 poly etch 설비에서의 고질 적인 문제이다. 발생 원인은 ElectroStatic Chuck(ESC)의 노후화 혹은process plasma에 의한 attack 등으로 ESC와 wafer간 dechucking이 진행될 때 wafer내의 전하가 완전히 discharge되지 못하여 wafer Sticking에 의한 sliding이 발생되며 심해지면 Dynamic Alignment(DA) Error가 발생한다. DA error 발생 되면 particle down으로 wafer는 scrap 되며 DA error가 지속적으로 발생하는 설비는 ESC 교체를 하고 있다. ESC 교체비용도 매우 크며 교체 전까지 설비가 멈추어있는 시간적인 손실이 발생하게 된다. Dechucking을 진행할 때 Wafer에 잔존하는 전하를 제거 하여 Wafer의 sticking을 줄여 DA error를 근원적으로 방지하기 위해 plasma를 이용하여 wafer와 ESC를 하나의 electric circuit으로 연결시키는 방법으로 wafer에 잔존하는 전하를 제거 시키고자 하였다.

• Journal of the Korean Ceramic Society
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• v.46 no.1
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• pp.30-34
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• 2009

A Sand blasting technology has been used to address via and trench processing of glass wafer of optic semiconductor packaging. Manufactured sand blast that is controlled by blast nozzle and servomotor so that 8" wafer processing may be available. 10mm sq test device manufactured by Dry Film Resist (DFR) pattern process on 8" glass wafer of $500{\mu}m's$ thickness. Based on particle pressure and the wafer transfer speed, etch rate, mask erosion, and vertical trench slope have been analyzed. Perfect 500 um tooling has been performed at 0.3 MPa pressure and 100 rpm wafer speed. It is particle pressure that influence in processing depth and the transfer speed did not influence.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.6 no.4
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• pp.34-38
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• 1997

This paper presents a joining method by using the silicon wafer in order to apply to joint to the 3-dimensional structures of semiconductor device, high-speed , high integration, micro machine, silicon integrated sensor, and actuator. In this study, the high atomic beam, stabilized by oxidation film and organic materials at the material surface, is investigated, and the purified is obtained by removing the oxidation film and pollution layer at the materials. And the unstable surface is obtained, which can be easily joined. In order to use the low temperatures for the joint method, the main subjects are obtained as follows: 1) In the case of the silicon wafer and the silicon wafer and the silicon wafer of alumina sputter film, the specimens can be jointed at 2$0^{\circ}C$, and the joining strength is 5Mpa. 2) The specimens can not always be joined at the room temperatures in the case of the silicon wafer and the silicon wafer of alumina sputter film.

• Journal of Korean Institute of Industrial Engineers
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• v.41 no.3
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• pp.267-274
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• 2015

In the semiconductor manufacturing post-FAB process, predicting a package test result accurately in the wafer testing phase is a key element to ensure the competitiveness of companies. The prediction of package test can reduce unnecessary inspection time and expense. However, an analysing method is not sufficient to analyze data collected at wafer testing phase. Therefore, many companies have been using a summary information such as a mean, weighted sum and variance, and the summarized data reduces a prediction accuracy. In the paper, we propose an analysis method for Wafer Map Image collected at wafer testing process and conduct an experiment using real data.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.04a
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• pp.1068-1071
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• 2001

Recently, the minimum line width shows a tendancy to decrease and the multi-level to increase in semiconductor. Therefore, a planarization technique is needed, which chemical polishing(CMP) is considered as one of the most important process. CMP accomplishes a high polishing performance and a global planarization of high quality. But there are several defects in CMP such as microscratches, abrasive contaminations, and non-uniformity of polished wafer edges. Spin Etching can improve the defects of CMP. It uses abrasive-free chemical solution instead of slurry. Wafer rotates and chemical solution is simultaneously dispensed on a whole surface of the wafer. Thereby chemical reaction is occurred on the surface of wafer, material is removed. On this study, TEOS film is removed by CMP and Spin Etching, the results are estimated at a viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU).

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.10a
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• pp.164-167
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• 2002

The general dicing process cuts a semiconductor wafer to lengthwise and crosswise direction by using a rotating circular diamond blade. But inferior goods are made under the influence of several parameters in dicing process such as blade, wafer, cutting water and cutting conditions. Moreover we can not applicable this dicing method to GaN wafer, because the GaN wafer is harder than the other wafer such as SiO$_2$, GaAs, CaAsP, and AlCaAs. In order to overcome this problem, development of a new dicing process and determination of dicing parameters are necessary. This paper describes determination of several parameters - scribing depth, scribing force, scriber inclined angle, scribing speed, and factor for scriber replacement - for a new dicing machine using scriber.