• Journal of the Korean Vacuum Society
• /
• v.17 no.6
• /
• pp.518-522
• /
• 2008

The miniaturization of device size and multilevel interlayers have been developed by ULSI circuit devices. These submicron processes cause serious problems in conventional metallization due to the solubility of silicon and metal at the interface, such as an increasing contact resistance in the contact hole and interdiffusion between metal and silicon. Therefore it is necessary to implement a barrier layer between Si and metal. Thus, the size of multilevel interconnection of ULSI devices is critical metallization schemes, and it is necessary reduce the RC time delay for device speed performance. So it is tendency to study the Cu metallization for interconnect of semiconductor processes. However, at the submicron process the interaction between Si and Cu is so strong and detrimental to the electrical performance of Si even at temperatures below $200^{\circ}C$. Thus, we suggest the tungsten-carbon-nitrogen (W-C-N) thin film for Cu diffusion barrier characterized by nano scale indentation system. Nano-indentation system was proposed as an in-situ and nanometer-order local stress analysis technique.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2009.10a
• /
• pp.464-465
• /
• 2009

A new level shifter using n-channel aluminum-doped zinc tin oxide (AZTO) thin film transistors (TFTs) was proposed to integrate driving circuits on qVGA panels for mobile display applications. The circuit used positive feedback loop to overcome limitations of circuits designed with oxide TFTs which is depletion mode n-channel TFTs. The measured results shows that the proposed circuit shifts 10 V input voltage to 20 V output voltage and its power consumption is 0.46 mW when the supply voltage is 20 V and the operating frequency is 10 kHz.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.06a
• /
• pp.114-115
• /
• 2006

반도체 기술이 초고집적화 되어감에 따라 공정에서 선폭이 줄어들고, 박막을 다층으로 제조하는 것이 중요하게 되었다. 이와 같은 제조 공정 하에서는 Si 기판과 금속 박막간의 확산이 커다란 문제로 부각되어 왔다. 특히 Cu는 높은 확산성에 의하여 Si 기판과 접합에서 많은 확산에 의한 문제가 발생하게 되며. 또한 선폭이 줄어듦에 따라 고열이 발생하여 실리콘으로 spiking이 발생하게 된다. 이를 방지하기 위하여 우리는 3개의 화합물로 구성된 Tungsten-Carbon-Nitrogen (W-C-N) 확산방지막을 사용하였다. 실험은 물리적 기상 증착법 (PVD)으로 질소비율을 변화하며 확산방지막을 증착하였고, 이를 여러 온도에서 열처리하여 X-ray Diffraction 분석을 하였다.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2011.02a
• /
• pp.204-205
• /
• 2011

In thin film silicon solar cells, p-i-n structure is adopted instead of p/n junction structure as in wafer-based Si solar cells. PECVD is a most widely used thin film deposition process for a-Si:H or ${\mu}c$-Si:H solar cells. For best performance of thin film silicon solar cell, the dopant profiles at p/i and i/n interfaces need to be as sharp as possible. The sharpness of dopant profiles can easily achieved when using multi-chamber PECVD equipment, in which each layer is deposited in separate chamber. However, in a single-chamber PECVD system, doped and intrinsic layers are deposited in one plasma chamber, which inevitably impedes sharp dopant profiles at the interfaces due to the contamination from previous deposition process. The cross-contamination between layers is a serious drawback of a single-chamber PECVD system in spite of the advantage of lower initial investment cost for the equipment. In order to resolve the cross-contamination problem in single-chamber PECVD systems, flushing method of the chamber with NH3 gas or water vapor after doped layer deposition process has been used. In this study, a new plasma process to solve the cross-contamination problem in a single-chamber PECVD system was suggested. A single-chamber VHF-PECVD system was used for superstrate type p-i-n a-Si:H solar cell manufacturing on Asahi-type U FTO glass. A 80 MHz and 20 watts of pulsed RF power was applied to the parallel plate RF cathode at the frequency of 10 kHz and 80% duty ratio. A mixture gas of Ar, H2 and SiH4 was used for i-layer deposition and the deposition pressure was 0.4 Torr. For p and n layer deposition, B2H6 and PH3 was used as doping gas, respectively. The deposition temperature was $250^{\circ}C$ and the total p-i-n layer thickness was about $3500{\AA}$. In order to remove the deposited B inside of the vacuum chamber during p-layer deposition, a high pulsed RF power of about 80 W was applied right after p-layer deposition without SiH4 gas, which is followed by i-layer and n-layer deposition. Finally, Ag was deposited as top electrode. The best initial solar cell efficiency of 9.5 % for test cell area of 0.2 $cm^2$ could be achieved by applying the in-situ plasma cleaning method. The dependence on RF power and treatment time was investigated along with the SIMS analysis of the p-i interface for boron profiles.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2005.02a
• /
• pp.58-58
• /
• 2005

• 한국초전도학회:학술대회논문집
• /
• v.11
• /
• pp.17-17
• /
• 2001

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1996.11a
• /
• pp.71-74
• /
• 1996

Ta$_2$O$_{5}$ film ale recognized as promising capacitor dielectric for future DRAM\`s. The electrical properties of Ta$_2$O$_{5}$films greatly depend on the heating condition. In the practical fabrication process, several annealing process, such as the annealing of Al in H$_2$(about 40$0^{\circ}C$) and reflow of BPSG (borophosphosilicate glass) film in $N_2$(about 80$0^{\circ}C$), exist after deposition of Ta$_2$O$_{5}$ film. In this paper, we describe the temperature effect on the electrical properties of W/Ta$_2$O$_{5}$/Si structure. The thin film of Ta$_2$O$_{5}$ and tungsten have been deposited on p-si(100) wafer using the sputtering system. The heating temperature was varied from 500 to 90$0^{\circ}C$ in $N_2$for 30min and The degree of temperature is 100\`C. In a log(J/E$^2$) Vs 1/E plot of typical I-V data, we find a linear relationship for the temperature of 500, $600^{\circ}C$ and as deposition. This could indicate Fowler-Nordheim tunneling as the dominant mode of current transports. However, we can not find a linear relationship for the temperature above $700^{\circ}C$. This could not indicate Fowler-Nordheim tunneling as the dominant mode of current transport. The high frequency (1MHz) capacitance-voltage (C-V) of W/Ta$_2$O$_{5}$/Si Capacitor were investigated on the basis of shift in the threshold voltage and dielectric constant. The magnitude of the threshold voltage and dielectric constant depends on the heating temperature, and increases with heating temperature.temperature.

• Journal of the Microelectronics and Packaging Society
• /
• v.14 no.1
• /
• pp.27-31
• /
• 2007

The cpapcitors with MIM(metal-insulator-metal) structures using PVP gate insulation films were prepared for the application of flexible organic thin film transistors (OTFT). The co-polymer organic insulation films were synthesized by using PVP(poly-4-vinylphenol) as a solute and PGMEA(propylene glycol monomethyl ether acetate) as a solvent. The cross-linked PVP insulation films were also prepared by addition of poly(melamine-co-formaldehyde) as thermal hardener. The leakage current of the cross- linked PVP films was found to be about 1.3 nA on Al/PES(polyethersulfone) substrate, whereas, on ITO/ glass substrate was about 27.5 nA indicating improvement of the leakage current at Al/PES substrates. Also, the capacitances of all prepared samples on ITO/glass and Al/PES substrates w ere ranged from 1.0 to $1.2nF/cm^2$, showing very similar result with the calculated capacitance values.

• Korean Journal of Materials Research
• /
• v.9 no.12
• /
• pp.1155-1159
• /
• 1999

Thin film solar cells on a glass/$SnO_2$ substrate with p-SiC/i-Si/n-Si heterojunction structures were fabricated using a plasma-enhanced chemical-vapor deposition system. The photovoltaic properties of the solar cells were examined with varying the gas phase composition, x=$CH_4/\;(SiH_4+CH_4)$, during the deposition of the p-SiC layer. In the range of x=0~0.4, the efficiency of solar cell increased because of the increased band gap of the p-SiC window layer. Further increase in the gas phase composition, however, led to a decrease in the cell efficiency probably due to in the increased composition mismatch at the p-SiC/i-Si layers. As a result, the efficiency of a glass/$SnO_2$/p-SiC/i-SiC/i-Si/n-Si/Ag thin film solar cell with $1cm^2$ area was 8.6% ($V_{oc}$=0.85V, $J_{sc}$=16.42mA/$cm^2$, FF=0.615) under 100mW/$cm^2$ light intensity.

• Journal of the Korean Solar Energy Society
• /
• v.25 no.4
• /
• pp.1-11
• /
• 2005

The stoichiometric mixture of evaporating materials for the $CuInSe_2$ single crystal thin film was prepared from horizontal furnace. Using extrapolation method of X-ray diffraction patterns for the polycrystal $CuInSe_2$, it was found tetragonal structure whose lattice constant $a_0$ and $c_0$ were $5.783\;{\AA}$ and $11.621\;{\AA}$, respectively. To obtain the $CuInSe_2$ single crystal thin film, $CuInSe_2$ mixed crystal was deposited on throughly etched GaAs(100) by the HWE(Hot Wall Epitaxy) system. The source and substrate temperature were $620^{\circ}C$ and $410^{\circ}C$ respectively. The crystalline structure of $CuInSe_2$ single crystal thin film was investigated by the double crystal X-ray diffraction(DCXD). Hall effect on this sample was measured by the method of Van der Pauw and studied on carrier density and mobility depending on temperature. From Hall data, the mobility was likely to be decreased by impurity scattering in the temperature range 30 K to 100 K and by lattice scattering in the temperature range 100 K to 293 K. The temperature dependence of the energy band gap of the $CuInSe_2$ obtained from the absorption spectra was well described by the Varshni's relation, $E_g(T)=1.1851\;eV-(8.99{\times}10^{-4}\;eV/K)T^2/(T+153\;K)$. The open-circuit voltage, short current density, fill factor, and conversion efficiency of $n-CdS/p-CuGaSe_2$ heterojunction solar cells under $80\;mW/cm^2$ illumination were found to be 0.51V, $29.3\;mA/cm^2$, 0.76 and 14.3 %, respectively.