• 한국전기전자재료학회논문지
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• 제15권3호
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• pp.233-237
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• 2002

A giga-bit DRAM(dynamic random access memory) technology with W/WNx/poly-Si dual gate electrode is presented in 7his papers. We fabricated $0.16\mu\textrm{m}$ CMOS using this technology and succeeded in suppressing short-channel effects. The saturation current of nMOS and surface-channel pMOS(SC-pMOS) with a $0.16\mu\textrm{m}$ gate was observed 330 $\mu\A/\mu\textrm{m}$ and 100 $\mu\A/\mu\textrm{m}$ respectively. The lower salutation current of SC-pMOS is due to the p-doped poly gate depletion. SC-pMOS shows good DIBL(dram-induced harrier lowering) and sub-threshold characteristics, and there was no boron penetration.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.193-196
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• 2002

This paper presents the improvement of the boron penetration and the reverse short channel effect (RSCE) in the 130nm W/WNx/Poly-Si dual gate PMOSFET for a high performance embedded DRAM. In order to suppress the boron penetration, we studied a range in the process heat budget. It has shown that the process heat budget reduction results in suppression of the boron penetration. To suppress the RSCE, we experimented with the halo (large tilt implantation of the same type of impurities as those in the device well) implant condition near the source/drain. It has shown that the low angle of the halo implant results in the suppression of the RSCE. The experiment was supported from two-dimensional(2-D) simulation, TSUPREM4 and MEDICI.

• 한국재료학회지
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• 제10권1호
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• pp.29-33
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• 2000

비정질 WNx 박막이 반응성 스퍼터링법으로 제조되었다. 비정질 형성을 위한 질소의 농도범위는 10~40at%이었다. 비정질 W(sub)67N(sub)33 박막은 1273K에서 1분 동안 급속 열처리되어 저항이 낮은 등축정의 $\alpha$-텅스텐 상과 과잉의 질소로 변태되었다. 이러한 박막의 저항은 순수한 텅스텐 박막과 유사하였다. $\alpha$-텅스텐 상으로부터 방출된 과잉의 질소는 $\alpha$-텅스텐/다결정 실리콘의 계면에 편석되었다. 편석된 질소는 Si$_3$N$_4$나노 결정으로 균일한 확산 장벽층을 형성시켰고, 저항이 높은 텅스텐 실리사이드의 반응을 억제하였다.