• Journal of Sensor Science and Technology
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• v.26 no.5
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• pp.331-337
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• 2017

A readout circuit for a tactile sensor pad based on force sensing resistors was proposed, which was composed of an analog signal conditioning circuit and a digital circuit with a microcontroller. The conventional signal conditioning circuit has a dc offset voltage in the output signal, which results from the reference voltage applied to the FSR devices. The offset voltage reduces the dynamic range of the circuit and makes it difficult to operate the circuit under a low voltage power supply. In the proposed signal conditioning circuit, the dc offset voltage was removed completely. The microcontroller with A/D converter and D/A converter was used to enlarge the measurement range of pressure. For this, the microcontroller adjusts the FSR reference voltage according to the resistance magnitude of FSR under pressure. The operation of the proposed readout circuit which was connected to a tactile sensor pad with $5{\times}10$ FSR array was verified experimentally. The experimental results show the proposed readout circuit has the wider measurement range of pressure than the conventional circuit. The proposed circuit is suitable for low voltage and low power applications.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.2B no.3
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• pp.81-89
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• 2002

The sensorless AC motor drive is a popular topic of study due to the cost and reliability of speed and position sensors. Most sensorless algorithms are based on the mathematical modeling of motors including electrical variables such as phase current and voltage. Therefore, the accuracy of such variables largely affects the performance of the sensorless AC motor drive. However, the output voltage of the SVPWM-VSI, which is widely used in sensorless AC motor drives, has considerable errors. In particular, the SVPWM-VSI is error-prone in the low speed range because the constant DC link voltage causes poor resolution in a low output voltage command and the output voltage is distorted due to dead time and voltage drop. This paper investigates a novel high-performance strategy for overcoming these problems in a sensorless ac motor drive. In this paper, a variation of the DC link voltage and a direct compensation for dead time and voltage drop are proposed. The variable DC link voltage leads to an improved resolution of the inverter output voltage, especially in the motor's low speed range. The direct compensation for dead time and voltage drop directly calculates the duration of the switching voltage vector without the modification of the reference voltage and needs no additional circuits. In addition, the proposed strategy reduces a current ripple, which deteriorates the accuracy of a monitored current and causes torque ripple and additional loss. Simulation and experimentation have been performed to verify the proposed strategy.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.316-324
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• 2010

In this paper, we design a 256 kbits EEPROM for a MCU (Microcontroller unit) with the wide voltage range of 1.8 V to 5.5 V. The memory space of the EEPROM is separated into a program and data region. An option memory region is added for storing user IDs, serial numbers and so forth. By making HPWs (High-voltage P-wells) of EEPROM cell arrays with the same bias voltages in accordance with the operation modes shared in a double word unit, we can reduce the HPW-to-HPW space by a half and hence the area of the EEPROM cell arrays by 9.1 percent. Also, we propose a page buffer circuit reducing a test time, and a write-verify-read mode securing a reliability of the EEPROM. Furthermore, we propose a DC-DC converter that can be applied to a MCU with the wide voltage range. Finally, we come up with a method of obtaining the oscillation period of a charge pump. The layout size of the designed 256 kbits EEPROM IP with MagnaChip's 0.18 ${\mu}m$ EEPROM process is $1581.55{\mu}m{\times}792.00{\mu}m$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.4
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• pp.34-42
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• 2012

In this paper, a wide-input range CMOS multi-mode rectifier for wireless power transfer system is presented. The output voltage of multi-mode rectifier is sensed by comparator and switches are controlled based on it. The mode of multi-mode rectifier is automatically selected by the switches among full-wave rectifier, 1-stage voltage multiplier and 2-stage voltage multiplier. In full-wave rectifier mode, the rectified output DC voltage ranges from 9 V to 19 V for a input AC voltage from 10 V to 20 V. However, the input-range of the multi-mode rectifier is more improved than that of the conventional full-wave rectifier by 5V, so the rectified output DC voltage ranges from 7.5 V to 19 V for a input AC voltage from 5 V to 20 V. The power conversion efficiency of the multi-mode rectifier is 94 % in full-wave rectifier mode. The proposed multi-mode rectifier is fabricated in a $0.35{\mu}m$ CMOS process with an active area of $2500{\mu}m{\times}1750{\mu}m$.

• Journal of the Korean Institute of Telematics and Electronics
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• v.13 no.6
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• pp.7-11
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• 1976

A voltage-stable negative resistance circuit with operational amplifier is proposed, and circuit analysis is given all the input voltage range. The behavior of the v-i characteristics in the nogative resistance region is devided into two causes, and top points in the input v-i characteristics of the circuit is analyzed with them. Experimental results of the v-i characteristics of the proposed circuit has a good linearity in the negative region with negative resistance, -86$\Omega$~-833$\Omega$ for the input voltage, $\pm$ 1~$\pm$ 5 colts. The v-i characteristics of the circuit in all the input voltage range is discussed.

• Proceedings of the KIPE Conference
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• 1996.06a
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• pp.71-75
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• 1996

As the Three-level ZVS PWM DC-DC converter operates likewise full-bridge ZVS PWM DC-DC converter and the blocking voltage of each switching device is a half of the DC-link voltage, it is suitable for the high imput voltage applications. However, it has some problems as follows; The blocking voltage of each devices is unbalanced and it causes the power losses of the inner switching devices to be increased. Also, it has narrow load range so that the switching losses and the efficiency are reduced as it goes to the light load. This paper presents an nove Three-level ZVS PWM DC-DC converter, which can reduce the overvoltage of the outer switches, eliminate the unbalance of the voltage sharing between the switches at turn-off due to the stray inductances, and operate from no load to full load. The characteristics and the performances of the proposed Three-level ZVS PWM DC-DC converter are verified by simulation and experimental results

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.6
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• pp.1596-1603
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• 1996

A single body type of fiber-optic current and voltae sensor using a rare earth doped YIG and a bismuth silicon oxide single crystsl is proposed, which is used for simultaneous measurement of the AC electric current and AC electric voltage over the trasmission lines. Experimental results showed that the fiber-optic current sensor has the maximum 7.5% error within the current range of 0A to 400A, and the fiber-optic voltage sensor has the maximum 0.87% error within the current range of 0V to 400V. The output waveforms of proposed fiber-optic sensor system has a good agreement with output waveforms of conductor current and voltage. Experimental results proved that the output of fiber-optic current sensor is not affected by the electric voltage applied to the fiber-optic voltage sensor, and also, that the output of fiber-optic voltage sensor is not affected by the electric current applied to the fiber-optic current sensor.

• Korean Chemical Engineering Research
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• v.61 no.1
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• pp.58-61
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• 2023

The activation process is essential for PEMFC to improve initial performance. The most commonly used activation method is a voltage change (load change) method, which may accompany degradation of the electrode catalyst if excessively performed. In many activation processes, the voltage change range is activated in a wide range from 0.4 V to OCV, and research is needed to reduce the voltage change range in order to prevent electrode catalyst degradation and shorten the activation time. Therefore, in this study, when the activation voltage range was 0.4~0.6 V, 0.4~0.8 V, and 0.4~OCV, we tried to research and develop an effective activation method by analyzing the performance and characteristics of the electrode and polymer membrane. The performance improvement was the lowest in the activation with a wide voltage range from 0.4 V to the highest OCV, and the performance decreased by 10% when activated for 56 cycles. The 0.4~0.6 V activation cycle showed the highest performance improvement up to 20% and the smallest decrease in performance due to overactivation, indicating that it is optimal method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.777-788
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• 2014

This paper presents a wide output range, high power efficiency reconfigurable charge pump for driving touch panels with the high resistances. The charge pump is composed of 4-stages and its configuration automatically changes based on the required output voltage level. In order to keep the power efficiency over the wide output voltage range, internal blocks are automatically activated or deactivated by the clock driver in the reconfigurable charge pump minimizing the switching power loss due to the On and Off operations of MOSFET. In addition, the leakage current paths in each mode are blocked to compensate for the variation of power efficiency with respect to the wide output voltage range. This chip is fabricated using $0.18{\mu}m$ BCD process with high power MOSFET options, and the die area is $1870{\mu}m{\times}1430{\mu}m$. The power consumption of the charge pump itself is 79.13 mW when the output power is 415.45 mW at the high voltage mode, while it is 20.097 mW when the output power is 89.903 mW at the low voltage mode. The measured maximum power efficiency is 84.01 %, when the output voltage is from 7.43 V to 12.23 V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.4
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• pp.303-309
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• 2013

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82mW with a single power supply of 1.2V and achieves 4.9 effective number of bits for input frequency up to 1MHz at 500 MS/s. Therefore it results in 4.75pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.