• Nuclear Engineering and Technology
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• v.51 no.4
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• pp.1091-1097
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• 2019

After the Fukushima accident in 2011, there has been increased public concern about radioactive contamination of water resources through fallout in neighboring countries. However, there is still no available initial response system that can promptly detect radionuclides. The purpose of this research is to develop the most efficient gamma spectrometer to monitor radionuclides in an aquatic environment. We chose a thallium-doped sodium iodide (NaI(Tl)) scintillator readout with a silicon photo multiplier (SiPM) due to its compactness and low operating voltage. Three types of a scintillation detector were tested. One was composed of a scintillator and a photomultiplier tube (PMT) as a reference; another system consisted of a scintillator and an array of SiPMs with a light guide; and the other was a scintillator directly coupled with an array of SiPMs. Among the SiPM-based detectors, the direct coupling system showed the best energy resolution at all energy peaks. It achieved 9.76% energy resolution for a 662 keV gamma ray. Through additional experiments and a simulation, we proved that the light guide degraded energy resolution with increasing statistical uncertainty. The results indicated that the SiPM-based scintillation detector with no light guide is the most efficient design for monitoring radionuclides in an aquatic environment.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.4 s.346
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• pp.75-80
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• 2006

This paper has proposed a novel dual band transmitter module which can be operating either as an amplifier or as a frequency multiplier according to the input frequency. A conventional dual band transmitter consists of separate amplifiers operating at each frequency band, but the proposed dual band module operates as an amplifier for the IEEE 802.11b/g signal, and as a frequency doubler for the IEEE 802.11a signal according to input frequency and bias voltage. In this paper, we have obtained sharp stop band characteristics by using microstrip DGS(Defected Ground Structure) to suppress the fundamental frequency of the frequency doubler as well as the second harmonic of the amplifier. From measurement result, second harmonic suppression is below -59dBc in the amplifier mode, and fundamental suppression is below -35dBc in the frequency doubler mode. And the designed module has 17.8dBm output P1dB at 2.4GHz and 10.1dBm power for 5.8GHz output, and the output power in the two modes are 0.8dB and 2.8dB larger than the module with ${\lambda}g/4$ reflector, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1627-1634
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• 2021

This paper introduces a low-power compact ADC circuit for analog Convolutional filter for low-power neural network accelerator SOC. While convolutional neural network accelerators can speed up the learning and inference process, they have drawback of consuming excessive power and occupying large chip area due to large number of multiply-and-accumulate operators when implemented in complex digital circuits. To overcome these drawbacks, we implemented an analog convolutional filter that consists of an analog multiply-and-accumulate arithmetic circuit along with an ADC. This paper is focused on the design optimization of a low-power 8bit SAR ADC for the analog convolutional filter accelerator We demonstrate how to minimize the capacitor-array DAC, an important component of SAR ADC, which is three times smaller than the conventional circuit. The proposed ADC has been fabricated in CMOS 65nm process. It achieves an overall size of 1355.7㎛², power consumption of 2.6㎼ at a frequency of 100MHz, SNDR of 44.19 dB, and ENOB of 7.04bit.