• Journal of IKEEE
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• v.10 no.1 s.18
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• pp.69-74
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• 2006

In this paper, we present symbol detection methods for decision feedback equalizers (DFE) in trellis coded modulation systems. The proposed symbol detectors improve symbol error rate (SER) by exploiting the coding structure of trellis coded modulation (TCM). For example, for 8-PAM signals the achieved SER with the proposed detection scheme is improved to $2{\times}10^{-5}$ from $2.5{\times}10^{-2}$ of the conventional symbol-by-symbol detector under AWGN channel at 20dB SNR. This SER improvements mitigate error propagation of DFE.and produces significant over-all SER improvement for under multipath channels (for example, from 0.26 to 0.01 and 0.005 under a severe multipath channel 20dB SNR as shown in the simulation result of this paper).

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.2039-2042
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• 2002

In this paper, we propose a technique used to simplify the trellis diagram, thus, reduce the complexity of Viterbi decoder in term of the number of Compare-Select (CS) operations needs in decoding process. It is shown that if the branch metrics are properly decomposed into orthogonal components. The trellis diagram can be modified that each original state with large number branches terminating to it can be broken into a number of sub-states having smaller number of branches terminating to them. Simulation results shown that the newly proposed technique can be used reduced the complexity of 8 and 16 PSK-TCMs without degrading the BER performance.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.11
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• pp.650-656
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• 2003

A high speed Viterbi decoder with a circularly connected 2-dimensional analog processing ceil array Is proposed. The proposed Viterbi .decoder has a 2-dimensional parallel processing structure in which an analog processing cell is placed at each node of a trellis diagram, the output column of the analog processing cells is connected to the decoding column, and thus, the output(last) column becomes a column right before the decoding(first) column. The reference input signal given at a decoding column is propagated to the whole network while Its magnitude is reduced by the amount of a error metric on each branch. The circuit-based decoding is done by adding a trigger signals of same magnitudes to disconnect the path corresponding to logic 0 (or 1) and by observing its effect at an output column (the former column of the decoding column). The proposed Viterbi decoder has advantages in that it is operated with better performance of error correction, has a shorter latency and requires no path memories. The performance of error correction with the proposed Viterbi decoder is tested via the software simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4C
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• pp.448-453
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• 2004

Conventional pragmatic TCMs need sector phase quantizer to apply Viterbi decoder which uses 3-bit soft decision. A symbol transformation applied to the incoming I-channel and Q-channel symbols allows to use Viterbi decoder without sector phase quantizer. We analyzed structure and performance of proposed decoder, and applied it to the turbo decoder. We know that the performance of proposed decoder is better than that of conventional decoder by 1 ［㏈］because of increasing of Euclidean distance.

• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.5
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• pp.583-586
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• 2004

Transition jitter noise is one of major sources of detection errors in high density recording channels. Implementation complexity of the optimal detector for such channels is high due to the data dependency and correlated nature of the jitter noise. In this paper, two types of hardware efficient sub-optimal detectors are derived by modifying branch metric of Viterbi algorithm and applied to partial response (PR) channels combined with run length limited modulation coding. The additional complexity over the conventional Viterbi algorithm to incorporate the modified branch metric is either a multiplication or an addition for each branch metric in the Viterbi trellis.

• Journal of Advanced Navigation Technology
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• v.8 no.2
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• pp.190-196
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• 2004

The development of a new hardware structure which can implement the viterbi algorithm efficiently is required for applications such as a software radio because the viterbi algorithm, which is an error correction code function for the second and the third generation of mobile communication, needs a lot of arithmetic operations. The length of K in the viterbi algorithm different from each standard, for examples, K=7 in case of IS-95 standard and GSM standard, and K=9 in case of WCDMA and CDMA2000. In this paper, we propose a new hardware structure of an adaptive viterbi decoder which can decode the constraint length in K=3~9 and the data rate in 1/2 ~ 1/3. Prototyping results targeted to Altera Cyclon EPIC20F400C8, shows that the proposed hardware structure needs maximum 19,276 logic elements and power dissipation of 222.6 mW.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.147-150
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• 2004

In this paper, we propose a reduced-state sequence estimation (RSSE) for trellis coded modulation (TCM) in OFDM with two-stage IDFT/ DFTs, MMSE-LE, and interleaving on frequency selective Rayleigh fading channels. The Viterbi algorithm (VA) is used to search for the best path through the reduced-state trellis combined with equalization and TCM decoding. Computer simulations confirm the bit error probability of the proposed scheme.

• Proceedings of the Acoustical Society of Korea Conference
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• 1998.06e
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• pp.211-214
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• 1998

TCM(Trellis-Coded Modulation)은 대역폭과 전력이 제한된 채널환경에서 채널부호화 기술과 변조기술을 결합시켜 대역폭의 증가없이 에러정정능력을 개선시키는 통신 기술이다. 본 논문에서는 TCM 신호의 복호시 사용되는 Viterbi decoder에서 traceback depth의 감소에 따른 BER(Bit Error Rate)의 증가를 개선하기 위해 수신부에서 설정하는 traceback depth를 주기로 blocking하여 TCM encoder의 입력시퀀스에 zero padding bits를 추가시키는 새로운 알고리듬을 제안한다. 모의실험결과, traceback depth가 50인 hard decision의 경우 약 2~2.5dB, 4-level soft decision과 8-level soft decision의 경우 약 0.3~2dB의 coding gain을 얻을 수 있었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.2
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• pp.86-91
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• 2014

Holographic data storage (HDS) has a number of advantages, including a high transmission rate through the use of a charge coupled device array for reading two-dimensional (2D) pixel image data, and a high density capacity. HDS also has disadvantages, including 2d intersymbol interference by neighboring pixels and interpage interference by multiple pages stored in the same holographic volume. These problems can be eliminated by modulation codes. We propose a 7/9 error-correcting modulation code that exploits a Viterbi-trellis algorithm and has a code rate larger (about 0.778) than that of the conventional 6/8 balanced modulation code. We show improved performance of the bit error rate with the proposed scheme compared to that of the simple 7/9 code without the trellis scheme and the 6/8 balanced modulation code.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.4
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• pp.24-31
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• 1995

In this paper, the dual-mode burst-error-correcting decoding algorithm is adapted to the multiple trellis-coded .pi./4 shift QPSK in order to achieve the improvement of bit error rate (BER) performance over fading channels. The dual-mode adaptive decoder which combines maximum likelihood decoding with a burst detection scheme usually operates as a Viterbi decoder and switches to time diversity error recovery whenever an uncorrectable error pattern is identified. Rayleigh fading channels and Rician fading channels having the Rician parameter K=5dB are used in computer simulation, and the simulation results are compared with those of interleaving techniques. It is shown that under the constraint of the fixed overall memory quantity, the dual-mode adaptive decoding scheme gains an advantage in the BER performance with respect to interleaving strategies.