• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.10B
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• pp.1732-1743
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• 2000

In this paper a fixed-delay trellis search with decision feedback (FDTrS/DF) for high-density DVD systems (4.7-15GB) is proposed and implemented with FPGA. The proposed FDTrS/DF is derived by transforming the binary tree search structure into trellis search structure implying that FDTrS/DF performs better than the singnal detection techniques based on tree search structure such as FDTS/DF and SSD/DF. Advantages of FDTrS/DF are significant reductions in hardware complexity due to the unique structure of FDTrS composed of only one trellis stage requiring no traceback procedure usually implemented in the Viterbi detector. Also in this paper the PDFS/DF and SSD/DF orginally proposed for high-density magnetic recording systems are modified for the DVD system and compared with the proposed FDTrS/DF. In order to increase speed in the FPGA implementation the pipelining technique and absolute branch metric (instead of square branch metric) are applied. The proposed FDTrS/DF is shown to provide the best performance among various signal detection techniques such as PRML, DFE, FDTS/DF and SSD/DF even with a small hardware complexity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2373-2379
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• 2015

COMS(Communication, Ocean and Meteorological Satellite), the first Korean geostationary meteorological satellite, provides free meteorological information through HRIT/LRIT(High/Low Rate Information Transmission) service. This work presents the development of data receiver circuit that is essential to the implementation of a low-cost meteorological information receiver system. The data receiver circuit processes the data units according to the specification of physical layer and data link layer of HRIT/LRIT service. For this purpose, the circuit consists of a Viterbi decoder, a sync. word detector, a derandomizer, a Reed-Solomon decoder and so on. The circuit also supports PCI express interface to pass the information data on to the host PC. The circuit was implemented on an FPGA(field programmable gate array) and its function was verified through simulations and hardware implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12C
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• pp.1601-1605
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• 2004

When codeword sequence has two or less successive transitions, the performance of 4th-order partial response maximum-likelihood (PRML) detector can be improved. However, the code leads to an unacceptable loss of performance due to the low code rate. For a rate 718 code that MTR constraint (i) of each codeword is limited to 2, and j is allowed to be 3 when codewords are connected, we modified the trellis of PRML detector to combine j=2 with J=3. We confirmed that the rate 718 coded 4th-order PRML detection with combined trellis achieves the SNR gain more than 2dB compared to the rate 819 coded 4u_order PRML detection at 10-s BER in high-density longitudinal or perpendicular magnetic recording systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.28-33
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• 2007

The front-end system having a capable of 2x reading and writing of BD-R/Ra/ROM is developed. Its readability is improved by adopting 5-tap adaptive partial response maximum likelihood (PRML) with the PR(a,b,c,d,e) type channel. Due to the proposed PRML, less than $2{\times}10^{-4}$ of the bit error rate (BER) is achieved with radial and tangential tilt margin of over${\mp}0.6{\circ}$ on 25GB disc in 2x speed. The method of an optimum Power control (OPC) for stable writing of various BD-R/RE is proposed. The developed chip contains 14-million transistors in a $60mm^2$ dies, and is fabricated in $0.18-{\mu}m$ CMOS technology.

• Journal of IKEEE
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• v.10 no.1 s.18
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• pp.69-74
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• 2006

In this paper, we present symbol detection methods for decision feedback equalizers (DFE) in trellis coded modulation systems. The proposed symbol detectors improve symbol error rate (SER) by exploiting the coding structure of trellis coded modulation (TCM). For example, for 8-PAM signals the achieved SER with the proposed detection scheme is improved to $2{\times}10^{-5}$ from $2.5{\times}10^{-2}$ of the conventional symbol-by-symbol detector under AWGN channel at 20dB SNR. This SER improvements mitigate error propagation of DFE.and produces significant over-all SER improvement for under multipath channels (for example, from 0.26 to 0.01 and 0.005 under a severe multipath channel 20dB SNR as shown in the simulation result of this paper).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.10C
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• pp.927-932
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• 2006

We Propose a partial response maximum likelihood(PRML) detection method that improves the performance of the high-density optical storage system. It concurrently adjusts the coefficient of equalizer and reference values of branches in Viterbi detector. For the estimation of asymmetric channel characteristics by the tangential tilt, we exploit sync patterns in each data frame. The simulation result shows it improves the Performance up to 4dB at 10-6 BER compared to conventional adaptive PRML.

• Nuclear Engineering and Technology
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• v.51 no.6
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• pp.1616-1625
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• 2019

Measuring occurrence times of random events, aimed to determine the statistical properties of the governing stochastic process, is a basic topic in science and engineering, and has been the subject of numerous mathematical modeling approaches. Often, true statistical properties deviate from measured properties due to the so called dead time phenomenon, where for a certain time period following detection, the detection system is not operational. Understanding the dead time effect is especially important in radiation measurements, often characterized by high count rates and a non-reducible detector dead time (originating in the physics of particle detection). The effect of dead time can be interpreted as a suitable rarefied sequence of the original time sequence. This paper provides a limit theorem for a high rate (diffusion-scale) counter with extendable (Type II) dead time, where the underlying counting process is a renewal process with finite second moment for the inter-event distribution. The results are very general, in the sense that they refer to a general inter arrival time and a random dead time with general distribution. Following the theoretical results, we will demonstrate the applicability of the results in three applications: serially connected components, multiplicity counting and measurements of aerosol spatial distribution.

• Journal of Korea Multimedia Society
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• v.12 no.3
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• pp.329-334
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• 2009

When an optical disc is being played. the pick-up converts light to analog signal at first. The analog signal is equalized for removing the inter-symbol interference and then the equalized analog signal is converted into the digital signal for extracting the synchronized data and clock signals. There are a lot of algorithms that minimize the BER in extracting the synchronized data and clock when high. density optical disc like BD is being played in low speed. But if the high-density optical disc is played in high speed, it is difficult to adopt the same extraction algorithm to data PLL and PRML architecture used in low speed application. It is because the signal with more than 800MHz should be processed in those architectures. Generally, in the 0.13-${\mu}m$ CMOS technology, it is necessary to have the high speed analog cores and lots of efforts to layout. In this paper, the parallel data PLL and PRML architecture, which enable to process in BD 8x speed of the maximum speed of the high-density optical disc as the extracting data and clock circuit, is proposed. Test results show that the proposed architecture is well operated without processing error at BD 8x speed.