• Title/Summary/Keyword: Viterbi Decoder

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Design of a convolutional encoder and viterbi cecoder ASIC for continuous and burst mode communications (연속 및 버스트모드 통신을 위한 길쌈부호기와 비터비복호기 ASIC 설계)

  • 장대익;김대영
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.4
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    • pp.984-995
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    • 1996
  • Data errors according to the various noises caused in the satellite communication links are corrected by the Viterbi decoding algorithm which has extreme error correcting capability. In this paper, we designed and implemented a convolutional encoder and Viterbi decoder ASIC which is used to encode the input data at the transmit side and correct the errors of the received data at the receive side for use in the VSAT communication system. And this chip may be used in any BPSK, QPSK, or OQPSK transmission system. The ambiguity resolver corrects PSK modem ambiguities by delaying, interting, and/or exchanging code symbol to restore their original sequence and polarity. In case of previous decoding system, ambiguity state(AS) of data is resolved by external control logic and extra redundancy data are needed to resolve AS. But, by adopting decoder proposed in this paper, As of data is resolved automatically by internal logic of decoder in case of continuous mode, and by external As line withoug extra redudancy data in burst mode case. So, decoding parts are simple in continuous mode and transmission efficiency is increased in bust mode. The features of this chip are full duplex operation with independent transmit and receive control and clocks, start/stop inputs for use in burst mode systems, loopback function to verify encoder and decoder, and internal or external control to resolve ambinguity state. For verification of the function and performance of a fabricated ASIC chip, we equiped this chip in the Central and Remote Earth Station of VSAT system, and did the performance test using the commerical INTELSAT VII under the real satellite link environmens. The results of test were demonstrated the superiority of performance.

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A Method of Multi-processing of ACS and Survivor Path Metric Memory Management for TCM Decoder (TCM 복호기의 ACS 다중화 및 생존경로척도 기억장치 관리 방법)

  • 최시연;강병희;김진우;오길남;김덕현
    • Proceedings of the IEEK Conference
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    • 2001.09a
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    • pp.865-868
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    • 2001
  • TCM offers considerable coding gains without compromising bandwidth or signal power. But TCM decoder is more complex than convolutional Viterbi decoder. Because, the number of branches exponentially increased by the constraint length and input symbol bits. The parallelism of ACS and memory management technique of SPMM is one of the important factor for speed-up and hardware complexity. This paper proposes a multi-processing technique of ACS and also gives a memory management technique of SPMM in TCM decoders.

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Trace-Back Viterbi Decoder with Sequential State Transition Control (순서적 역방향 상태천이 제어에 의한 역추적 비터비 디코더)

  • 정차근
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.40 no.11
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    • pp.51-62
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    • 2003
  • This paper presents a novel survivor memeory management and decoding techniques with sequential backward state transition control in the trace back Viterbi decoder. The Viterbi algorithm is an maximum likelihood decoding scheme to estimate the likelihood of encoder state for channel error detection and correction. This scheme is applied to a broad range of digital communication such as intersymbol interference removing and channel equalization. In order to achieve the area-efficiency VLSI chip design with high throughput in the Viterbi decoder in which recursive operation is implied, more research is required to obtain a simple systematic parallel ACS architecture and surviver memory management. As a method of solution to the problem, this paper addresses a progressive decoding algorithm with sequential backward state transition control in the trace back Viterbi decoder. Compared to the conventional trace back decoding techniques, the required total memory can be greatly reduced in the proposed method. Furthermore, the proposed method can be implemented with a simple pipelined structure with systolic array type architecture. The implementation of the peripheral logic circuit for the control of memory access is not required, and memory access bandwidth can be reduced Therefore, the proposed method has characteristics of high area-efficiency and low power consumption with high throughput. Finally, the examples of decoding results for the received data with channel noise and application result are provided to evaluate the efficiency of the proposed method.

Differential space-time coded OFDM using multiple symbol decoding (다중 심벌 디코딩을 이용한 차동 시공간 부호화된 OFDM)

  • Yoo Hang-Youal;Kim Seung-Youal;Kim Chong-Il
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.3 no.1 s.4
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    • pp.117-125
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    • 2004
  • Space-time coding and modulation exploit the presence of multiple transmit antennas to improve performance on multipath Rayleigh fading channels. In this paper, we propose the Trellis-Coded Differential Space Time Modulation-OFDM system with multiple symbol detection. The Trellis-code perform the set partition with unitary group codes. The Viterbi decoder containing new branch metrics is introduced in order to improve the bit error rate (BER) in the differential detection of the Unitary differential space time modulation. Also, we describe the Viterbi algorithm in order to use this branch metrics. Our study shows that such a Viterbi decoder improves BER performance without sacrificing bandwidth and power efficiency.

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Improved Differential Detection Scheme of Space-Time Trellis Coded MDPSK For MIMO (MIMO에서 시공간 부호화된 MDPSK의 성능을 향상시키기 위한 차동 검파 시스템)

  • Kim, Chong-Il;Lee, Ho-Jin;Yoo, Hang-Youal;Kim, Jin-Yong;Kim, Seung-Youal
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.10
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    • pp.1869-1876
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    • 2006
  • Recently, STC techniques have been considered to be candidate to support multimedia services in the next generation mobile radio communications and have been developed the many communications systems in order to achieve the high data rates. In this paper, we Nose the Trellis-Coded Differential Space Time Modulation system with multiple symbol detection. The Trellis-code performs the set partition with unitary group codes. The Viterbi decoder containing new branch metrics is introduced in order to improve the bit error rate (BER) in the differential detection of the unitary differential space time modulation. Also, we describe the Viterbi algorithm in order to use this branch metrics. Our study shows that such a Viterbi decoder improves BER performance without sacrificing bandwidth and power efficiency.

Multiple Symbol Detection of Trellis coded Differential space-time modulation for OFDM (OFDM에서 트렐리스 부호화된 차동 시공간 변조의 다중 심벌 검파)

  • 유항열;한상필;김진용;김성열;김종일
    • Journal of the Institute of Convergence Signal Processing
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    • v.5 no.3
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    • pp.223-229
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    • 2004
  • Recently, OFDM and STC techniques have been considered to be candidate to support multimedia services in the next generation mobile radio communications and have been developed the many communications systems in order to achieve the high data rates. In this paper, we propose the Trellis-Coded Differential Space Time Modulation-OFDM system with multiple symbol detection. The Trellis-code performs the set partition with unitary group codes. The Viterbi decoder containing new branch metrics is introduced in order to improve the bit error rate (BER) in the differential detection of the unitary differential space time modulation. Also, we describe the Viterbi algorithm in order to use this branch metrics. Our study shows that such a Viterbl decoder improves BER performance without sacrificing bandwidth and power efficiency.

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Implementation of Radix-2 structure to reduce chip size (Chip면적 감소를 위한 Radix-2구조 구현)

  • 최영식;한대현
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 1999.05a
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    • pp.407-410
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    • 1999
  • Viterbi decoder is implemented with a Radix-4 architecture at 0.5$\mu\textrm{m}$ process even though the delay time of standard tell is big and it causes a bigger chip size. As process develops, the delay time of standard cells is getting smaller. Therefore, the requirement of speed and chip size is satisfied by using Radix-2 algorithm to implement Viterbi decoder.

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Performance Enhancement of Multi-Band OFDM using Spectrum Equalizer

  • Yoon, Sang-Hun;Jung, Jun-Mo
    • Journal of information and communication convergence engineering
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    • v.8 no.6
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    • pp.687-689
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    • 2010
  • In this paper, the equalization for frequency slope of path loss in Multi-Band(MB) OFDM UWB is proposed. The path loss of a signal is proportionate to the square of the signal's frequency. So, the received signal amplitudes of OFDM subcarrier can be different up to 3dB when MB-OFDM occupies bandwidth over 1.5GHz. The differences of subcarrier-amplitudes make an effective of 0.3 bit reduction of soft decision bits of viterbi decoder, and when the effective of 0.3 bit reduction can cause 0.5dB SNR degradation. This paper proposes two modem architectures which compensate for the degraded subcarrier by multiplying the reciprocal of degraded values in analog or digital domain. It is shown that, for the proposed architecture applied to MB-OFDM UWB, the performance improvements up to 0.5dB can be obtained over the conventional uncompensated receiver architecture.

New soft-output MLSE equalization algorithm for GSM digital cellular systems

  • 한상성;노종선;정윤철;김관옥;신윤복;함승재;이상봉
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.3
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    • pp.747-752
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    • 1996
  • In this paper, we propose a new SO-MLSE(soft-output maximum likelihood sequence estimation) equalizer, which can be used in GSM digital cellular system) it uses complex correlation of training sequence to obtain the channel information and the equalization is performed by MLSE using Viterbi algorithm. In order to generate a soft-decision input to channel decoder (Viterbi decoder), the soft-output equalization algorithm is needed. The adopted algorithm doesn't require to modify the structure of HO-MLSE(hard output MLSE) equalizer, that is, SO-MLSE equalizer can be implemented by adding soft-output generation block to HO-MLSE equalizer. This algorithm uses the outputs of matched filter and HO-MLSE equalizer. It turns out that the complexity of proposed SO-MLSE equalizer is simpler than those of other SO-MLSE equalizer and its perforance is almost the same as those of others. Finally, the proposed SO-MLSE equalizer is also implemented s a prototype with ADSP-2101 16-bits fixed point digital signal processing chip.

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