• Journal of IKEEE
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• v.19 no.2
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• pp.254-259
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• 2015

CABAC is a context-based adaptive binary arithmetic coding method. It increases the encoding efficiency by updating the probability based on the information of the previously coded symbols. Context modeler is a core block of CABAC, which designs a probability model according to the symbol considering statistical correlations. In this paper, an efficient hardware architecture of CABAC context modeler is proposed. The proposed context modeler was designed in Verilog HDL and it was implemented in 0.18 um technology. Its gate count is 29,832 gates including memory. Its operating speed and throughput are 200 MHz and 200 Mbin/s, respectively.

• Journal of IKEEE
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• v.21 no.3
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• pp.240-243
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• 2017

CAN (controller area network) suffers from data bottleneck since the number of in-vehicle electronic modules significantly increases. To mitigate this problem, CAN-FD (CAN with flexible data rate) has been proposed. Transmission speed is same with CAN in arbitration phase but much higher than CAN in data phase, which successfully achieves both compatibility and efficiency. In this paper, a CAN-FD controller was designed in Verilog HDL and it was implemented and verified in FPGA. The designed controller can perform CAN-FD version 1.0 and CAN version 2.0A, 2.0B. Synthesized in 0.18um technology, its size is about 46,300 gates.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6C
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• pp.594-600
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• 2002

A data manipulation unit capable of bit partitioned shift and various multimedia data type conversions in addition to conventional shift, is presented. Utilizing the similarity between the data type conversion and the shift, the addition of small amount of interconnections to conventional barrel shifter enables data type conversion as well as shift operations with minimal hardware overhead. The presented data manipulation unit is composed of the shifter block for conventional shift and a pack and a unpack block. It has been designed with verilog HDL and the VLSI implementation results using compass 0.6 um standard cell are discussed.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.1
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• pp.239-245
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• 2019

RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. In this paper, according to the emergence of RISC-V architecture, we describe the RISC-V processor instruction set constituted by arithmetic logic, memory, branch, control, status register, environment call and break point instructions. Using ModelSim and Quartus-II, 38 instructions of RISC-V has been successfully simulated and synthesized.

• Journal of IKEEE
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• v.27 no.4
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• pp.501-511
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• 2023

This paper introduces and analyzes SAE J2716 SENT (Single Edge Nibble Transmission) protocol, a technical standard for serial transmission of digital sensor data in automotive applications. SENT can transmit both high-speed sensor data and low-speed sensor data in one data frame and has a total of 6 transmission modes, including 3 high-speed channel modes and 3 low-speed channel modes. In this paper, a SENT controller that supports all six modes of the SENT protocol was designed in Verilog HDL, implemented in FPGA, and verified with an oscilloscope and PC.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.6C
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• pp.777-784
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• 2004

In this paper, a new filter structure to improve frequency response characteristics in decimation filter using CIC(Cascaded Integrator-Comb) filters and half band filters is proposed. Conventional filters improve only passband characteristics, but we propose a new filter which can improve stop band and pass band characteristics simultaneously. Since proposed filter needs only two multiplication, additional implementation cost is not much. And overall linear phase characteristics are maintained since the proposed filter is also linear phase. Finally, filter coefficients quantization effects ate discussed after Verilog-HDL coding.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.138-144
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• 2013

In XRF systems, various techniques have been developed for the synthesis of pulse shapes using digital methods instead of traditional analog methods. Trapezoidal pulse shaping algorithms can be used for digital multi-channel pulse height analysis in X-ray spectrometer systems. In this paper, an efficient trapezoidal filter architecture is presented. In addition, we present a hardware-efficient peak value detection algorithm. By the proposed algorithm, peak value detection error is decreased by half compared with the conventional algorithm. The proposed Digital Pulse Processing(DPP) algorithm is designed using Verilog HDL and implemented using an FPGA on a test board. It is demonstrated that the implemented DPP board works successfully in practical XRF systems.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.11
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• pp.97-104
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• 2010

This paper presents a high performance 32-bit single core AES architecture. The proposed architecture employs a 5-stage pipeline: four stages in the ShiftRows/InvShiftRows module, and one stage in the MixColumn/InvMixColumn module. Circuit size reduction has been achieved through merging of the shift rows and inverse shift rows. The mix column and inverse mix column share the same resources. Three 32-bit registers replace the conventional ten 32-bit registers in the RCON architecture. The proposed architecture has been implemented in Verilog HDL, and yields 415 Mbits/s throughput with the circuit size of 13764 gate equivalents on the 0.18um CMOS process technology. This high performance architecture is suitable for wireless network router applications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.12
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• pp.2725-2730
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• 2012

In this paper, for improving the H.264/AVC hardware performance, we propose an inter predictor hardware design using a multi reference frame selector and an implicit weighted predictor. previous reference frame are reused for Low Memory Bandwidth. The size of the reference memory in the predictor was reduced by about 46% and the external memory access rate was reduced by about 24% compared with the one in the reference software JM16.0. We designed the proposed system with Verilog-HDL and synthesized inter predictor circuit using the Magnachip 0.18um CMOS standard cell library. The synthesis result shows that the gate count is about 2,061k and the design can run at 91MHz.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.31-39
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• 1998

This paper presents the design and implementation of a new multimedia fixed-point DSP (MDSP) core for portable multimedia applications. The MDSP instruction set is designed through the analysis of multimedia algorithms and DSP instruction sets. The MDSP architecture employs parallel processing techniques, such as SIMD and vector processing as well as DSP techniques. The instruction set can handle various data formats and MDSP can perform two MAC operations in parallel. The switching network and packing network can increase the performance by overlapping data rearrangement cycles with computation cycles. We have designed Verilog HDL models and the 0.6 $\mu\textrm{m}$ Samsung KG75000 SOG library is used. The total gate count is 68,831 and the clock frequency is 30 MHz.