• Proceedings of the Korea Information Processing Society Conference
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• 2015.10a
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• pp.1571-1572
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• 2015

본 논문에서는 GMM (Gaussian mixture model) 기반의 BS (background subtraction) 알고리즘을 이용한 이동 객체 검출기의 하드웨어 구조 설계 결과를 제시하였다. 설계된 이동객체 검출기는 1280 * 720 HD 해상도의 영상을 30 frames per second로 실시간 처리가 가능하다. 하드웨어 구현은 Verilog-HDL을 이용하였으며, FPGA 기반 구현 결과, 설계된 이동 객체 검출기는 582 Slice, 1,698 Slice LUT, 8 DSP48s, 1,769 Flip Flop, 691.2 KByte BRAM으로 구성되었음을 확인하였다.

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.2
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• pp.100-107
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• 2011

As the use of mobile multimedia devices is increasing in the recent year, the needs for high-performance multimedia processors are increasing. In this regard, we propose a SIMD (Single Instruction Multiple Data) based parallel processor that supports high-performance multimedia applications with low energy consumption. The proposed parallel processor consists of 16 processing elements(PEs) and operates on a 3-stage pipelining. Experimental results for the JPEG encoding algorithm indicate that the proposed parallel processor outperforms conventional parallel processors in terms of performance and energy efficiency. In addition, the proposed parallel processor architecture was developed and verified with verilog HDL and a FPGA prototype system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.155-157
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• 2016

한국 표준 블록암호 알고리듬 ARIA(Academy, Research Institute, Agency)와 미국 표준인 AES(Advanced Encryption Standard) 알고리듬은 128-비트 블록 길이를 지원하고 SPN(substitution permutation network) 구조를 특징으로 가져 서로 유사한 형태를 지닌다. 본 논문에서는 ARIA와 AES를 선택적으로 수행하는 ARIA-AES 통합 프로세서를 효율적으로 구현하였다. Verilog HDL로 설계된 ARIA-AES 통합 프로세서를 Virtex5 FPGA로 구현하여 정상 동작함을 확인하였고, $0.18{\mu}m$ 공정의 CMOS 셀 라이브러리로 100KHz의 동작주파수에서 합성한 결과 39,498 GE로 구현되었다.

• Journal of Korea Society of Digital Industry and Information Management
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• v.10 no.4
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• pp.117-125
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• 2014

In this paper, a novel hardware architecture of the LT codec is presented where non-BP based decoding algorithm is applied. Novel LT codec architecture is designed with an efficient degree distribution unit using Verilog HDL. To perform permutation operation, different initial valued or time shifted counters have been used to get pretty well permutations and an effect of randomness. The codec will take 128 bits as input and produce 256 encoded output bits. The simulation results show expected performances as the implemented distribution and the original distribution are pretty same. The proposed LT codec takes 257.5 cycle counts and $2.575{\mu}s$ for encoding and decoding instead of 5,204,861 minimum cycle counts and 4.43s of the design mentioned in the previous works where iterative soft BP decoding was used in ASIC and ASIP implementation of the LT codec.

• Proceedings of the Korea Information Processing Society Conference
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• 2022.05a
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• pp.494-496
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• 2022

엣지 디바이스에서 딥러닝을 활용하기 위하여 CNN 경량화 연구들이 진행되고 있다. 경량 CNN 은 대부분 고정 소수점을 사용하며, 계층에 따라 정밀도는 달라진다. 본 논문에서는 경량 CNN 을 지원하기 위하여, 사용 계층에 따라 정밀도를 선택할 수 있는 가변 정밀도 곱셈기를 제안한다. 제안하는 가변 정밀도 곱셈기는 낮은 정밀도 곱셈기를 병합하는 구조로, 정밀도가 낮을 때는 병렬 처리를 통해 효율을 높인다. 제안하는 곱셈기를 Verilog HDL로 설계하고 ModelSim 에서 동작을 확인하였다. 설계된 곱셈기는 계층별로 정밀도가 다른 CNN 가속기에서 효율적으로 적용될 것으로 기대된다.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.08a
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• pp.265-268
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• 2000

In this paper, we propose an algorithm, an optimized architecture, and an implementation for an improved performance of image downscaler. The proposed downscaler uses two-dimensional digital filters for horizontal and vertical scalings, respectively. It also improves scaling precisions and decreases the loss of data, compared with the 1/32 scaler 〔1〕. In order to achieve the optimization, the digital filters are implemented by the multiplexer -adder type scheme 〔2〕. The scaler is designed by using the Verilog-HDL. It is synthesized into gates by using the Samsung 0.35 um STD90 TLM library.

• Proceedings of the Korea Information Processing Society Conference
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• 2008.11a
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• pp.1473-1476
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• 2008

본 논문에서는 RFID 시스템의 Tag와 Reader 사이의 보안상의 문제점을 해결하기 위하여 공격에 강인한 AES 암호 프로세서 기반 인증 프로토콜을 제안한다. 제안한 인증 프로토콜은 Reader에서 난수를 생성하고 Tag와 Reader 그리고 Back-End Server의 인증과 통신 데이터를 암호화 하여 기존의 보안상의 문제점을 개선하고, ISO/IEC 18000-3 표준 프로토콜을 기반으로하여 확장된 패킷 구조를 사용한다. 제안한 시스템은 Xilinx ISE 9.1i 환경에서 Verilog HDL을 사용하여 설계하였으며, 설계 검증은 Mentor 사의 Modelsim 6.2c를 사용하여 제안된 시스템이 정확히 동작함을 확인하였다.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.153-156
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• 2000

This paper presents a SOC design methodology using the newly-emerging SystemC. The suggested methodology firstly uses SystemC to define blocks from the previously-developed system level algorithm with internal behavior and interface being separated and validate such a described blocks' functionality when integrated. Next, the partitioning between software and hardware is considered. With software, the interface to hardware is described cycle-accurate and the other internal behavior in conventional ways. With hardware, I/O transactions are refined gradually in several abstraction levels and internal behavior described on a function basis. Once hardware and software have been completed functionally, system performance analysis is performed on the built model with assumed performance factors and influences such decisions regressively as on optimum algorithm selection, partitioning and etc. The analysis then gives constraint information when hardware description undergoes scheduling and fixed-point trans- formation with the help of automatic translation tools or manually. The methodology enables C/C++ program developers and VHDL/Verilog users to migrate quickly to a co-design & co-verification environment and is suitable for SoC development at a low cost.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.2
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• pp.78-84
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• 2000

The Viterbi decoders can be classified into serial Viterbi decoders and parallel Viterbi decoders. Parallel Viterbi decoders can handle higher data rates than serial Viterbl decoders. This paper designs and implements a fully parallel Viterbi decoder for high speed multimedia communications. For high speed operations, the ACS (Add-Compare-Select) module consisting of 64 PEs (Processing Elements) can compute one stage in a clock. In addition, the systolic away structure with 32 pipeline stages is developed for the TB (traceback) module. The implemented Viterbi decoder can support code rates 1/2, 2/3, 3/4, 5/6 and 7/8 using punctured codes. We have developed Verilog HDL models and performed logic synthesis. The 0.6 ${\mu}{\textrm}{m}$ SAMSUNG KG75000 SOG cell library has been used. The implemented Viterbi decoder has about 100,400 gates, and is running at 70 MHz in the worst case simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.2
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• pp.293-298
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• 2009

In this contribution, a 193-bit elliptic curve cryptography coprocessor was implemented on an FPGA board. Optimized algorithms and numerical expressions which had been verified through C program simulation, should be analyzed again with HDL (hardware description language) such as Verilog, so that the verified ones could be modified to be applied directly to hardware implementation. The reason is that the characteristics of C programming language design is intrinsically different from the hardware design structure. The hardware IP which was double-checked in view of hardware structure together with algoritunic verification, was implemented on the Altera CycloneII FPGA device equipped with ARM9 microprocessor core, to a real chip prototype, using Altera embedded system development tool kit. The implemented finite field calculation IPs can be used as library modules as Elliptic Curve Cryptography finite field operations which has more than 193 bit key length.