• Transactions of the Korean Society of Automotive Engineers
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• v.22 no.3
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• pp.68-74
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• 2014

As the number of ECUs (Electronic control units) are increasing, reliability and functional stability of a software in an ECU is getting more important. Therefore the application of functional safety standards ISO 26262 is making the software more reliable. Software fault injection test (SFIT) is required as a verification technique for the application of ISO 26262. In case of applying SFIT, an artificial error is injected to inspect the vulnerability of the system which is not easily detected during normal operation. In this paper, the basic concept of SFIT will be examined and the application of SIFT based on ISO26262 will be described.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.865-867
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• 2009

This paper is a research on the statistical analysis of the feature information for the dynamic signature verification. we could improved processing time and reduce signature database without increase of error rate. We have used statistical analysis method T-test for the verification based on the experimental results.

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.167-170
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• 2003

In this paper, a design and experiment of PCI Express Core verification Model is described. The model targeting Endpoint core verification is designed by using newly-emerging SystemC which is a system design language based on a new C++ class library and simulation engine. In the verification model, we developed a SystemC Host System model which act as a Root Complex and Device Driver dedicated to the PCI Express Endpoint RTL Core. The test of Host System Model is guided by scenarios which implements and acts point of Device Driver and Root Complex and shows the result of simulation. Also, We present the full structure of verification model and Host model.

• Journal of Information Processing Systems
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• v.12 no.3
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• pp.381-391
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• 2016

The Joint Bayesian (JB) method has been used in most state-of-the-art methods for face verification. However, since the publication of the original JB method in 2012, no improved verification method has been proposed. A lot of studies on face verification have been focused on extracting good features to improve the performance in the challenging Labeled Faces in the Wild (LFW) database. In this paper, we propose an improved version of the JB method, called the two-dimensional Joint Bayesian (2D-JB) method. It is very simple but effective in both the training and test phases. We separated two symmetric terms from the three terms of the JB log likelihood ratio function. Using the two terms as a two-dimensional vector, we learned a decision line to classify same and not-same cases. Our experimental results show that the proposed 2D-JB method significantly outperforms the original JB method by more than 1% in the LFW database.

• The Magazine of the IEIE
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• v.30 no.9
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• pp.1002-1011
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• 2003

In this paper, we introduce an integrated SoC front-end design & verification environment which can be practically used in the embedded 32-bit processor-core SoC VLSI design. Our introduced SoC design & verification environment integrates two most important flows, such as the RTL power estimation and code coverage analysis, with the functional verification (chip validation) flow which is used in the conventional simulation-based design. For this, we developed two simulation-based inhouse tools, RTL power estimator and code coverage analyzer, and used them to adopt them to our RTL design and to increase the design quality of that. Our integrated design environment also includes basic design and verification flows such as the gate-level functional verification with back annotation information and test vector capture & replay environment.

• The Journal of the Korea Contents Association
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• v.15 no.12
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• pp.1-7
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• 2015

These anti-jamming GPS systems are verified using large anechoic chamber or field-test until now. When using a large anechoic chamber, Independent verification from external enviroments like noise is an advantage but high cost and availability of chamber are disadvantages. And in case of field test, verification under real propagation enviroment is an advantage but security problem of military equipments and problem of making same test condition are disadvantages. This paper presents an newly developed anti-jamming GPS test system. This test system mainly consists of small anechoic chamber, jamming divider, jamming signal generator and satellite simulator. The small anechoic chamber is installed many jamming antennas to transmit multi jamming signals and the jamming divider is newly developed to control multi jamming signals. According to self performance test and combined test with Anti-jamming GPS receiver, we verified our system's reliability.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.2
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• pp.199-207
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• 2014

Although High-altitude electromagnetic pulse(HEMP) protection filter meets the requirements of pulsed current injection(PCI) acceptance test, the equipment under test which has low electromagnetic susceptibility level can be damaged during PCI verification test that is performed on operating condition of equipment. This paper proposed the HEMP effect analysis method using comparison of norms between residual current of HEMP filter and transient electromagnetic conducted susceptibility criteria of equipment, as an alternative method under the condition that performing PCI verification test is limited in HEMP hardened facilities. PCI acceptance test of HEMP filter, transient electromagnetic conducted susceptibility test, and PCI verification test are performed and test results are analyzed.

• Journal of the Korea Society for Simulation
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• v.20 no.4
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• pp.41-48
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• 2011

The act of writing a unit test is more an act of design than of verification. It is also more an act of documentation than of verification. The act of writing a unit test closes a remarkable number of feedback loops, the least of which is the one pertaining to verification of function. Unit testing is a fundamental practice in Extreme Programming, but most non-trivial code is difficult to test in isolation. Normal unit testing is hard because It is trying to test the code from outside. On the other hand, developing unit tests with Mock Objects leads to stronger tests and to better structure of both domain and test code. In this paper, I first describe how Mock Objects are used for unit testing of federation integration. Then I describe the benefits and costs of Mock Objects when writing unit tests and code. Finally I describe a design of Mock federate for using Mock objects.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.274-279
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• 2009

The flow of a universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In this paper, verification environments based-on SystemVerilog and SystemC, one is native-code co-verification environment which makes prompt functional verification possible and another is SystemVerilog layered testbench which makes clock-level verification possible, are implemented. In native-code co-verification, HW and SW parts of SoC are respectively designed with SystemVerilog and SystemC after HW/SW partitioning using SystemC, then the functional interaction between HW and SW parts is carried out as one simulation process. SystemVerilog layered testbench is a verification environment including corner case test of DUT through the randomly generated test-vector. We adopt SystemC to design a component of verification environment which has multiple inheritance, and we combine SystemC design unit with the SystemVerilog layered testbench using SystemVerilog DPI and ModelSim macro. As multiple inheritance is useful for creating class types that combine the properties of two or more class types, the design of verification environment adopting SystemC in this paper can increase the code reusability.

• Applied Chemistry for Engineering
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• v.9 no.7
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• pp.1023-1029
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• 1998

Small water leak experiment was carried out for the 5Cr-1Mo steel specimen in sodium atmosphere. Perfect re-open time for the leak path of a specimen, by micro leak, was 129 minutes, and its size observed about 2 mm diameter at sodium side. The halos phenomena appeared around of leak spot before the leak path has re-opened, and the size of halos observed was different from the real re-open size of a specimen. Also, the corrosion of a specimen initiated from sodium side, but it did not occur at steam side. In AES analysis, the segregation phenomena of Cr in the specimen was found much more than those of other elements. And also, the sodium compounds formed by sodium-water reaction and deposited onto the leak site of specimen were observed by EPMA analysis and SEM photograph. It is postulated that the corrosion products could be precipitated to form mixed Na Fe Cr compounds.