• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.917-920
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• 2005

This paper presents 3D graphics geometry processor for mobile applications. Geometry stage needs to cope with the large amount of computation. Geometry stage consists of transformation process and lighting process. To deal with computation in geometry stage, the vector processor that is based on pipeline chaining is proposed. The performance of proposed 3D graphics geometry processor is up to 4.3M vertex/sec at 100 MHz. Also, the designed processor is compliant with OpenGL ES that is widely used for standard API of embedded system. The proposed structure can be efficiently used in 3D graphics accelerator for mobile applications.

• The Journal of Information Technology
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• v.10 no.3
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• pp.33-45
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• 2007

Systolic Array Processor is used for designing the special purpose processor in Digital Signal Processing, Computer Graphics, Neural Network Applications etc., since it has the characteristic of parallelism, pipeline processing and architecture of regularity. But, in case of using general design method, it has intial waiting period as large as No. of PE-1. And if the connected system needs parallel and simultaneous outputs, processor has some problems of the performance, since it generates only one output at each clock in output state. So in this paper, one dimensional Systolic Array Processor that is designed according to the dependance of data and operations using the partitioned sub-matrix is proposed for the purpose of improving the performance. 1-D Systolic Array using 4 partitioned sub-matrix has efficient method in case of considering those two problems.

• Electronics and Telecommunications Trends
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• v.32 no.6
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• pp.57-65
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• 2017

Neural network based AI computing is a promising technology that reflects the recognition and decision operation of human beings. Early AI computing processors were composed of GPUs and CPUs; however, the dramatic increment of a floating point operation requires an energy efficient AI processor with a highly parallelized architecture. In this paper, we analyze the trends in processor architectures for AI computing. Some architectures are still composed using GPUs. However, they reduce the size of each processing unit by allowing a half precision operation, and raise the processing unit density. Other architectures concentrate on matrix multiplication, and require the construction of dedicated hardware for a fast vector operation. Finally, we propose our own inAB processor architecture and introduce domestic cutting-edge processor design capabilities.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.7
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• pp.1112-1120
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• 1994

This paper presents a servo control scheme for the surface-mounted permanent-magnet synchronous motor(SPMSM) which essentially uses vector control algorithm. The control system is composed of the PI controller for speed control and the current controller using space voltage vector PWM technique. The high-speed calculation and processing for vector control is carried out by TMS320C31 digital signal processor and IGBT module. The proposed scheme is verified through digital simulations and experiments for 2.2kW SPMSM and shows good dynamic performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.4
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• pp.727-736
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• 2009

In this paper, the $arccos(cos^{-1})$ arithmetic unit for mobile graphics accelerator is designed. The mobile vector graphics applications need tight area, execution time, power dissipation, and accuracy constraints compared to desktop PC applications. The designed processor adopts 2nd-order polynomial approximation scheme based on IEEE floating point data format to satisfy speed and accuracy conditions and reduces area via hardware sharing structure. The arccosine processor consists of 15,280 gates and its estimated operating frequency is about 125Mhz at operating condition of $0.35{\mu}m$ CMOS technology. Because the processor can execute arccosine function within 7 clock cycles, it has about 17 MOPS(million arccos operations per second) execution rate and can be applicable to mobile OpenVG processor. And because of its flexible architecture, it can be applicable to the various transcendental functions such as exponential, trigonometric and logarithmic functions via replacement of ROM and minor hardware modification.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.95-98
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• 2002

This paper presents a study on DSP(TMS320F240) controller design for multi-axes transportation system using BLDC servo motor. This BLDC servo motor controller was realized with DSP(Digital Signal Processor) and IPM (Intelligent Power Module). The multi-axes transportation system needs torque, speed, position control of servo motor for variable action. This paper implements those servo control with vector control and space vector modulation technique. As CPU of controller DSP(TMS320F240) is adopted because, it has PWM(Pulse Width Modulation) waveform generator, A/D(Analog to Digital) converter, SPI(Serial Peripheral Interface) port and input/output port etc. The controller of multi-axes transportation system consists of 3-level hierarchy structure that main host PC manages three sub DSP system which transfer downword command and are monitoring the states of end servo controllers. Each sub DSP system operates eight BLDC servo controllers which control BLDC servo motor using DSP and IPM Between host system and middle digital signal processor communicate with RS-422, between main processor and controller communicate with SPI port.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.6
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• pp.161-169
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• 2011

Recent intelligent video surveillance system asks for development of more advanced technology for analysis and recognition of video data. Especially, machine learning algorithm such as Support Vector Machine (SVM) is used in order to recognize objects in video. Because SVM training demands massive amount of computation, parallel processing technique is necessary to reduce the execution time effectively. In this paper, we propose a parallel processing method of SVM training with a multi-core processor. The results of parallel SVM on a 4-core processor show that our proposed method can reduce the execution time of the sequential training by a factor of 2.5.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1221-1224
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• 2003

A 64-point R2$^2$ SDF pipeline FFT processor using a new efficient computation sharing multiplier was designed. Computation sharing multiplication specifically targets computation re-use in multiplication of coefficient vector by scalar and is effectively used in DSP(Digital Signal Processing). To reduce the number of multipliers in FFT, we used the proposed computation sharing multiplier. The 64-point pipeline FFT processor was implemented by VHDL and synthesized using Max+PLUSII of Altera. The simulation result shows that the proposed computation sharing multiplier can be reduced to about 17.8% logic cells compared with a conventional multiplier. This processor can operate at 33MHz and calculate a 64-point pipeline FFT in 1.94 $mutextrm{s}$.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1102-1103
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• 2007

This Paper presents a solution to control the Brushless DC Motor(BLDCM) in Digital Lightening Processor(DLP) using the Linear Quadratic Regulator(LQR). Generally, The speed of BLDCM in DLP is controlled by the lead angle control or the input voltage control using PAM(Pulse Amplitude Modulation) etc. These control methods have speed overshoot in speed control and need the long time until BLDCM reaches at the steady state. In order to improve the performance, this paper present the PI speed controller using the LQR based on vector control and the rotor position detection methods at the space vector PWM inverter. The proposed methods are proved by the experimental results

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.9C
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• pp.851-859
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• 2003

최근 사용자들의 멀티채널 선호도는 급속도로 전파되고 있다. MPEG은 동영상 및 음향시스템의 데이터 압축기술을 제공하는데, 현재 각광을 받고있는 것이 디지털 오디오이다. MPEG 표준안은 MPEG-1오디오 알고리즘을 MPEG-2 알고리즘에 동일하게 사용해도 멀티채널 및 5.1채널 사운드륵 제공한다. MDCT(Modified Discrete Cosine Transform)는 TDAC(Time Domain Aliasing Cancellation)에 기반을 두고있는 변형이산 여현 변환을 나타낸 것이다. 본 논문에서는 오디오 부분의 핵심이라 할 수 있는 MDCT/IMDCT(Inverse MDCT) 알고리즘을 최적화하여 효율적인 알고리즘을 제안하였다. 그리고 연산과정에서 중복되는 영역을 묶음으로써 연산에 필요한 계수를 줄였다. 최적화 전에 비해 코사인 계수를 0.5%이하로 최적화하였고, 승산에서 0.098%, 가산에서 0.58% 효율을 보였다. 알고리즘 검증은 C언어를 사용하여 검증하였고, 최적화된 알고리즘을 적용하여 마이크로 프로그램 방식의 하드웨어 구조론 설계하였다.