• Proceedings of the IEEK Conference
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• 2000.06c
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• pp.133-136
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• 2000

A RVLC(Reversible Variable Length Code) with an efficient table memory is proposed in this paper. In the conventional decoding methods, the weight of symbols and code values are used for the decoding table. These methods can be applied for Huffman decoding. In VLC decoding, many studies have been done for memory efficiency and decoding speed. We propose an improved table construction method for general VLC and RVLC decoding, which uses the transition number of bits within a symbol with an enhanced weight decomposition. In this method, tile table for RVLC decoding can be implemented with a smaller memory

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.3
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• pp.316-324
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• 2001

A table compression method for reversible variable length code is proposed in this paper. TNWT(Transition Number and Weight of Tree) method, which uses the transition number of bits within a symbol and the level of a code tree, is proposed. Compression of table values is performed after arrangment of values that is not distinghishable by transition number and weights. In decoding, the transition number and weight of code are used. In this method, the table for RVLC decoding can be implemented with a smaller memory.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3C
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• pp.249-255
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• 2007

In general, a large amount of the memory accesses are required for the CAVLC decoding in H.264/AVC. It is a serious problem for the applications such as a DMB and videophone services because the considerable power is consumed for accessing the memory. In order to solve this problem, we propose an efficient decoding method for the coeff-token which is one of the syntax elements of CAVLC. In this paper, the variable length code table is re-designed with the new codewords which are defined by investigating the architecture of the conventional codeword for the coeff_token element. A new coeff_token decoding method is developed based on the suggested table. The simulation results show that the proposed algorithm achieves an approximately 85% memory access saving without video-quality degradation, compared to the conventional CAVLC decoding.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.7
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• pp.78-91
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• 1998

This paper presents modular design techniques of multiple-valued logic functions about the function decomposition method and input variable management method. The function decomposition method takes avantage of the property of the column multiplicity in a single-column variable partitioning. Due to the increased number of identical modules, we can achieve a simpler circuit design by using a single T-gate, which can eliminate some of the control functions in the module libraty types. The input variable management method is to reduce the complexity of the input variables by proposing the look up table which assign input variables to a code. In this case as the number of sub-functions increase the code-length and the size of the code-assignment table grow. We identify some situations where shard input variables among sub-functions can be further reduced by a simplicication technique. According to the result of adapting this method to a function, we have demonstrated the superiority of the proposed methods which is bing decreased to about 12% of interconnection and about 16% of T-gate numbers compare with th eexisting for th enon-symmetric and irregular function realization.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.1
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• pp.57-68
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• 2004

Although variable-length codes (VLCs) increase coding efficiency using the statistical characteristics of the source data, they have catastrophic effects from bit errors in noisy transmission environments. In order to overcome this problem with VLCs, reversible variable-length codes (RVLCS) have recently been proposed owing to their data recovering capability. RVLCS can be divided into two categories: symmetrical and asymmetrical RVLCs. Although the symmetrical RVLC has generally more overheads than the asymmetrical RVLC, it has some advantages of simpler design and more efficient memory usage. However, existing symmetrical RVLCs still have high complexity in their code design and some room for improvement in coding efficiency. In this paper, we propose a new algorithm for constructing a symmetrical RVLC from the optimal Huffman code table. The proposed algorithm has a simpler design process and also demonstrates improved performance in terms of the average codeword length relative to the existing symmetrical RVLC algorithms.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.108-111
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• 2008

In this paper, we propose an advanced hardware architecture for the CAVLC entropy encoder engine for real time Full HD video compression. Since there are 384 data coefficients which are sum of 376 AC coefficient and 8 DC coefficient per one macroblock, 384 coefficient have to be processed per one macroblock in worst case for real time processing. We propose an novel architecture which includes parallel architecture and pipeline processing, and reduction "0" in AC/DC coefficient table. To verify the proposed architecture, we develop the reference C for CAVLC and verified the designed circuit with the test vector from reference C code.

• IEMEK Journal of Embedded Systems and Applications
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• v.5 no.2
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• pp.77-83
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• 2010

In this paper, we propose an efficient memory architecture for coeff_token encoding in H.264/AVC standard. The VLCTs used to encode the coeff_token syntax element are implemented with the memory. In general, the size of memory must be reduced because it affects the cost and operation speed of the system. Based on the analysis for the codewords in VLCTs, new memory architecture is designed in this paper. The proposed memory architecture results in about 24% memory saving, compared to the conventional memory architecture.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.3
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• pp.80-80
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• 2001

본 논문에서는 가역가변길이 부호를 테이블 메모리에 효율적으로 저장하는 방법을 제안한다. 여러개의 부호들을 적은 개수의 값들로 테이블을 구성하는 새로운 알고리듬으로, 가역가변길이 부호의 부호내의 비트 천이개수와 부호 구성 트리에서의 레벨을 이용하는 TNWT(Transition Number and Weight of Tree)방법을 제안한다. 압축에 앞서 가역가변길이 부호들의 가중치와 천이개수를 구하고, 신장된 값들이 서로 구분이 안되는 경우를 방지하기 위해 테이블의 값들을 재배열한다. 재배열이 끝난 배열의 값들을 세 개씩 묶어 압축된 테이블을 얻는다. 압축된 테이블은 부호의 천이개수와 가중치를 이용하여 복호해 낼 수 있다. 이러한 방법을 통하여 기존의 방법보다 약 20% 적은 크기로 테이블 메모리를 구성하고, 압축된 테이블로 복호가 가능함을 확인하였다.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.7
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• pp.70-82
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• 1993

In this paper, employing the 3-dimensional discrete cosine transform (DCT) for the utilization of the temporal correlation, an adaptive motion sequence coding technique is proposed. The energy distribution in a 3-D DCT block, due to the nonstationary nature of the image data, varies along the veritical, horizontal and temporal directions. Thus, aiming an adaptive system to local variations, adaptive procedures, such as the 3-D classification, the classified linear scanning technique and the VLC table selection scheme, have been implemented in our approach. Also, a hybrid structure which adaptively combines inter-frame coding is presented, and it is found that the adaptive hybrid frame coding technique shows a significant performance gain for a moving sequence which contains a relatively small moving area. Through an intensive computer simulation, it is demonstrated that, the performance of the proposed 3-D transform coding technique shows a close relation with the temporal variation of the sequence to be code. And the proposed technique has the advantages of skipping the computationally complex motion compensation procedure and improving the performance over the 2-D motion compensated transform coding technique for rates in the range of 0.5 ~ 1.0 bpp.

• Journal of Advanced Navigation Technology
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• v.17 no.1
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• pp.69-79
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• 2013

In this paper, DCT(Discrete Cosine Transform) and CAVLC(Context Adaptive Variable Length Coding) are co-designed as hardware IP with software operation of the other modules in H.264/AVC codec. In order to increase the operation speed, a new method using SHIFT table is proposed. As a result, enhancement of about 16(%) in the operation speed is obtained. Designed Hardware IPs are downloaded into Virtex-4 FX60 FPGA in the ML-410 development board and H.264/AVC encoding is performed with Microblaze CPU implemented in FPGA. Software modules are developed from JM13.2 to make C code. In order to verify the designed Hardware IPs, Modelsim program is used for functional simulation. As a result that all Hardware IPs and software modules are downloaded into the FPGA, improvement of processing speed about multiples of 16 in case of DCT hardware IP and multiples of 10 in case of CAVLC compared with software-only processing. Although this paper deals with co-design of H/W and S/W for H.264, it can be utilized for the other embedded system design.