• Carbon letters
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• v.12 no.4
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• pp.207-217
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• 2011

We discuss the influence of few-walled carbon nanotubes (FWCNTs) treated with nitric acid and/or sulfuric acid on field emission characteristics. FWCNTs/tetraethyl orthosilicate (TEOS) thin film field emitters were fabricated by a spray method using FWCNTs/TEOS sol one-component solution onto indium tin oxide (ITO) glass. After thermal curing, they were found tightly adhered to the ITO glass, and after an activation process by a taping method, numerous FWCNTs were aligned preferentially in the vertical direction. Pristine FWCNT/TEOS-based field emitters revealed higher current density, lower turn-on field, and a higher field enhancement factor than the oxidized FWCNTs-based field emitters. However, the unstable dispersion of pristine FWCNT in TEOS/N,N-dimethylformamide solution was not applicable to the field emitter fabrication using a spray method. Although the field emitter of nitric acid-treated FWCNT showed slightly lower field emission characteristics, this could be improved by the introduction of metal nanoparticles or resistive layer coating. Thus, we can conclude that our spray method using nitric acid-treated FWCNT could be useful for fabricating a field emitter and offers several advantages compared to previously reported techniques such as chemical vapor deposition and screen printing.

• Journal of the Korean Ceramic Society
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• v.52 no.6
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• pp.441-448
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• 2015

Silicon carbide (SiC) coatings for tri-isotropic (TRISO) nuclear fuel particles were fabricated using a chemical vapor deposition (CVD) process onto graphite. A micro-tensile-testing system was developed for the mechanical characterization of SiC coatings at high temperatures. The fracture strength of the SiC coatings was characterized by the developed micro-tensile test in the range of $25^{\circ}C$ to $1000^{\circ}C$. Two types of CVD-SiC films were prepared for the micro-tensile test. SiC-A exhibited a large grain size (0.4 ~ 0.6 m) and the [111] preferred orientation, while SiC-B had a small grain size (0.2 ~ 0.3 mm) and the [220] preferred orientation. Free silicon (Si) was co-deposited onto SiC-B, and stacking faults also existed in the SiC-B structure. The fracture strengths of the CVD-SiC coatings, as measured by the high-temperature micro-tensile test, decreased with the testing temperature. The high-temperature fracture strengths of CVD-SiC coatings were related to the microstructure and defects of the CVD-SiC coatings.

• Journal of the Korean Ceramic Society
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• v.39 no.2
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• pp.171-177
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• 2002

In this study, the vertical aligned carbon nanotubes was synthesized by DC bias-assisted Inductively Coupled Plasma Hot-Filament Chemical Vapor Deposition (ICPHFCVD). The substrate used CNTs growth was Ni(300 ${\AA}$)/Cr(200 ${\AA}$)-deposited one on glass by RF magnetron sputtering. R-F, DC bias and filament power during the growth process were 150 W, 80 W, 7∼8 A, respectively. The grown CNTs showed hollow structure and multi-wall CNTs. The top of grown CNT was found to Ni-tip that the CNT end showed to metaltip. The graphitization and field emission properties of grown was better than grown CNTs by ICPCVD. The turn-on voltage of CNT grown by DC bias-assisted ICPHFCVD showed about 3 V/${\mu}m$.

• Proceedings of the Korea Association of Crystal Growth Conference
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• 1996.06a
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• pp.422-448
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• 1996

Low-temperature epitaxial growth of Si and SiGe layers of Si is one of the important processes for the fabrication of the high-speed Si-based heterostructure devices such as heterojunction bipolar transistors. Low-temperature growth ensures the abrupt compositional and doping concentration profiles for future novel devices. Especially in SiGe epitaxy, low-temperature growth is a prerequisite for two-dimensional growth mode for the growth of thin, uniform layers. UHV-ECRCVD is a new growth technique for Si and SiGe epilayers and it is possible to grow epilayers at even lower temperatures than conventional CVD's. SiH and GeH and dopant gases are dissociated by an ECR plasma in an ultrahigh vacuum growth chamber. In situ hydrogen plasma cleaning of the Si native oxide before the epitaxial growth is successfully developed in UHV-ECRCVD. Structural quality of the epilayers are examined by reflection high energy electron diffraction, transmission electron microscopy, Nomarski microscope and atomic force microscope. Device-quality Si and SiGe epilayers are successfully grown at temperatures lower than 600℃ after proper optimization of process parameters such as temperature, total pressure, partial pressures of input gases, plasma power, and substrate dc bias. Dopant incorporation and activation for B in Si and SiGe are studied by secondary ion mass spectrometry and spreading resistance profilometry. Silicon p-n homojunction diodes are fabricated from in situ doped Si layers. I-V characteristics of the diodes shows that the ideality factor is 1.2, implying that the low-temperature silicon epilayers grown by UHV-ECRCVD is truly of device-quality.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.19 no.6
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• pp.298-304
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• 2009

The effect of the surface treatments on the high temperature properties of the Inconel 617, one of the promising candidate alloys for high temperature heat-transport system, has been studied. Various surface modification methods including a rapid thermal process(RTP), a hydrothermal treatment, and a physical vapor deposition($2{\mu}m$ thick TiAlN film by an arc discharge) were applied to the Inconel 617. The morphological and the structural properties of the surface-modified Inconel 617 samples after heat treatment at $1000^{\circ}C$ in the air were compared to find out whether inhomogeneous formation of $Cr_2O_3$ crust at the surface region was suppressed or not. TiAlN-coated Inconel 617 showed homogeneous microstructure and the lowest wear loss compared to bare, RTP- and hydrothermally-treated Inconel 617 by suppressing the $Cr_2O_3$ crust formation.

• Transactions on Electrical and Electronic Materials
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• v.8 no.3
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• pp.110-114
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• 2007

Dependence of the thermal stability of nickel silicide on the film stress of inter layer dielectric (ILD) layer has been investigated in this study and silicon nitride $(Si_3N_4)$ layer is used as an ILD layer. Nickel silicide was formed with a one-step rapid thermal process at $500^{\circ}C$ for 30 sec. $2000{\AA}$ thick $Si_3N_4$ layer was deposited using plasma enhanced chemical vapor deposition after the formation of Ni silicide and its stress was split from compressive stress to tensile stress by controlling the power of power sources. Stress level of each stress type was also split for thorough analysis. It is found that the thermal stability of nickel silicide strongly depends on the stress type as well as the stress level induced by the $Si_3N_4$ layer. In the case of high compressive stress, silicide agglomeration and its phase transformation from the low-resistivity nickel mono-silicide to the high-resistivity nickel di-silicide are retarded, and hence the thermal stability is obviously improved a lot. However, in the case of high tensile stress, the thermal stability shows the worst case among the stressed cases.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.7
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• pp.85-94
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• 1994

A high-resolution transmission electron microscopy study of the solid phase crystallization of the amorphous silicon thin films, deposited on SiOS12T at 52$0^{\circ}C$ by low pressure chemical vapor deposition and annealed at 55$0^{\circ}C$ in a dry N$_{2}$ ambient was carried out so that the arrangement of atoms in the crystalline silicon and at the amorphous/crystalline interface of the growing grains could be understood on an atomic level. Results show that circular crystalline silicon nuclei have formed and then the grains grow to an elliptical or dendritic shape. In the interior of all the grains many twins whose{111} coherent boundaries are parallel to the long axes of the grains are observed. From this result, it is concluded that the twins enhance the preferential grain growth in the <112> direction along {111} twin planes. In addition to the twins. many defect such as intrinsic stacking faults, extrinsic stacking faults, and Shockley partial dislocations, which can be formed by the errors in the stacking sequence or by the dissociation of the perfect dislocation are found in the silicon grain. But neither frank partial dislocations which can be formed by the condensation of excess silicon atoms or vacancies and can form stacking fault nor perfect dislocations which can be formed by the plastic deformation are observed. So it is concluded that most defects in the silicon grain are formed by the errors in the stacking sequence during the crystallization process of the amorphous silicon thin films.

• 한국태양에너지학회:학술대회논문집
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• 2012.03a
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• pp.243-247
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• 2012

The paper focuses on an anti-reflection (AR) coating deposited by PECVD in silicon solar cell fabrication. AR coating is effective to reduce the reflection of the light on the silicon wafer surface and then increase substantially the solar cell conversion efficiency. In this work, we carried out experiments to optimize double AR coating layer with silicon nitride and silicon oxide for the silicon solar cells. The p-type mono crystalline silicon wafers with $156{\times}156mm^2$ area, 0.5-3 ${\Omega}{\cdot}cm$ resistivity, and $200{\mu}m$ thickness were used. All wafers were textured in KOH solution, doped with $POCl_3$ and removed PSG before ARC process. The optimized thickness of each ARC layer was calculated by theoretical equation. For the double layer of AR coating, silicon nitride layer was deposited first using $SiH_4$ and $NH_3$, and then silicon oxide using $SiH_4$ and $N_2O$. As a result, reflectance of $SiO_2/SiN_x$ layer was lower than single $SiN_x$ and then it resulted in increase of short-circuit current and conversion efficiency. It indicates that the double AR coating layer is necessary to obtain the high efficiency solar cell with PECVD already used in commercial line.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.361.2-361.2
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• 2014

Transition metal dichalcogenides (MoS2, WS2, WSe2, MoSe2, NbS2, NbSe2, etc.) are layered materials that can exhibit semiconducting, metallic and even superconducting behavior. In the bulk form, the semiconducting phases (MoS2, WS2, WSe2, MoSe2) have an indirect band gap. Recently, these layered systems have attracted a great deal of attention mainly due to their complementary electronic properties when compared to other two-dimensional materials, such as graphene (a semimetal) and boron nitride (an insulator). However, these bulk properties could be significantly modified when the system becomes mono-layered; the indirect band gap becomes direct. Such changes in the band structure when reducing the thickness of a WS2 film have important implications for the development of novel applications, such as valleytronics. In this work, we report for the controlled synthesis of large-area (~cm2) single-, bi-, and few-layer WS2 using a two-step process. WOx thin films were deposited onto a Si/SiO2 substrate, and these films were then sulfurized under vacuum in a second step occurring at high temperatures ($750^{\circ}C$). Furthermore, we have developed an efficient route to transfer these WS2 films onto different substrates, using concentrated HF. WS2 films of different thicknesses have been analyzed by optical microscopy, Raman spectroscopy, and high-resolution transmission electron microscopy.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.165-165
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• 2014

In this study, we demonstrated that the soft lithographic patterning processing of chemical vapor deposition (CVD) graphene and rGO sheets as large scale, low cost, high quality and simplicity for future industrial applications. Recently, a previous study has reported that single layer graphene grown via CVD was patterned and transferred to a target surface by controlling the surface energy of the polydimethylsiloxane (PDMS) stamp [1]. Using this approach, the surface of a relief-patterned elastomeric stamp was functionalized with hydrophilic dimethylsulfoxide (DMSO) molecules to enhance the surface energy of the stamp and to remove the graphene-based layer from the initial substrate and transfer it to a target surface [2]. Further, we developed a soft lithographic patterning process via surface energy modification for advanced graphene-based flexible devices such as transistors or simple and efficient chemical sensor consisting of reduced graphene oxide (rGO) and a metallic nanoparticle composite. A flexible graphene-based device on a biocompatible silk fibroin substrate, which is attachable to an arbitrary target surface, was also successfully fabricated.