• Title/Summary/Keyword: Vacuum leakage

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Study of Capacitorless 1T-DRAM on Strained-Silicon-On-Insulator (sSOI) Substrate Using Impact Ionization and Gate-Induced-Dran-Leakage (GIDL) Programming

  • Jeong, Seung-Min;Jeong, Hong-Bae;Lee, Yeong-Hui;Jo, Won-Ju
    • Proceedings of the Korean Vacuum Society Conference
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    • 2011.08a
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    • pp.285-285
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    • 2011
  • 최근 반도체 소자의 미세화에 따라, 단채널 효과에 의한 누설전류 및 소비전력의 증가 등이 문제되고 있다. 대표적인 휘발성 메모리인 dynammic random access memory (DRAM)의 경우, 소자의 집적화가 진행됨에 따라 저장되는 정보의 양을 유지하기 위해 캐패시터영역의 복잡한 공정을 요구하게 된다. 하나의 캐패시터와 하나의 트랜지스터로 이루어진 기존의 DRAM과 달리, single transistor (1T) DRAM은 silicon-on-insulator (SOI) 기술을 기반으로 하여, 하나의 트랜지스터로 DRAM 동작을 구현한다. 이러한 구조적인 이점 이외에도, 우수한 전기적 절연 특성과 기생 정전용량 및 소비 전력의 감소 등의 장점을 가지고 있다. 또한 strained-Si 층을 적용한 strained-Silicon-On-Insulator (sSOI) 기술을 이용하여, 전기적 특성 및 메모리 특성의 향상을 기대 할 수 있다. 본 연구에서는 sSOI 기판위에 1T-DRAM을 구현하였으며, impact ionization과 gate induced-drain-leakage (GIDL) 전류에 의한 메모리 구동 방법을 통해 sSOI 1T-DRAM의 메모리 특성을 평가하였다. 그 결과 strain 효과에 의한 전기적 특성의 향상을 확인하였으며, GIDL 전류를 이용한 메모리 구동 방법을 사용했을 경우 낮은 소비 전력과 개선된 메모리 윈도우를 확인하였다.

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Memory Characteristics of High Density Self-assembled FePt Nano-dots Floating Gate with High-k $Al_2O_3$ Blocking Oxide

  • Lee, Gae-Hun;Lee, Jung-Min;Yang, Hyung-Jun;Kim, Kyoung-Rok;Song, Yun-Heub
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.388-388
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    • 2012
  • In this letter, We have investigated cell characteristics of the alloy FePt-NDs charge trapping memory capacitors with high-k $Al_2O_3$ dielectrics as a blocking oxide. The capacitance versus voltage (C-V) curves obtained from a representative MOS capacitor embedded with FePt-NDs synthesized by the post deposition annealing (PDA) treatment process exhibit the window of flat-band voltage shift, which indicates the presence of charge storages in the FePt-NDs. It is shown that NDs memory with high-k $Al_2O_3$ as a blocking oxide has performance in large memory window and low leakage current when the diameter of ND is below 2 nm. Moreover, high-k $Al_2O_3$ as a blocking oxide increases the electric field across the tunnel oxide, while reducing the electric field across the blocking layer. From this result, this device can achieve lower P/E voltage and lower leakage current. As a result, a FePt-NDs device with high-k $Al_2O_3$ as a blocking oxide obtained a~7V reduction in the programming voltages with 7.8 V memory.

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Thermal Stability of Self-formed Barrier Stability Using Cu-V Thin Films

  • Han, Dong-Seok;Mun, Dae-Yong;Kim, Ung-Seon;Park, Jong-Wan
    • Proceedings of the Korean Vacuum Society Conference
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    • 2011.02a
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    • pp.188-188
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    • 2011
  • Recently, scaling down of ULSI (Ultra Large Scale Integration) circuit of CMOS (Complementary Meta Oxide Semiconductor) based electronic devices, the electronic devices, become much faster and smaller size that are promising property of semiconductor market. However, very narrow interconnect line width has some disadvantages. Deposition of conformal and thin barrier is not easy. And metallization process needs deposition of diffusion barrier and glue layer for EP/ELP deposition. Thus, there is not enough space for copper filling process. In order to get over these negative effects, simple process of copper metallization is important. In this study, Cu-V alloy layer was deposited using of DC/RF magnetron sputter deposition system. Cu-V alloy film was deposited on the plane SiO2/Si bi-layer substrate with smooth surface. Cu-V film's thickness was about 50 nm. Cu-V alloy film deposited at $150^{\circ}C$. XRD, AFM, Hall measurement system, and AES were used to analyze this work. For the barrier formation, annealing temperature was 300, 400, $500^{\circ}C$ (1 hour). Barrier thermal stability was tested by I-V(leakage current) and XRD analysis after 300, 500, $700^{\circ}C$ (12 hour) annealing. With this research, over $500^{\circ}C$ annealed barrier has large leakage current. However vanadium-based diffusion barrier annealed at $400^{\circ}C$ has good thermal stability. Therefore thermal stability of vanadium-based diffusion barrier is desirable for copper interconnection.

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Electrical properties of $(Ba,Sr)TiO_3$ thin films and conduction mechanism of leakage current ($(Ba,Sr)TiO_3$박막의 전기적 성질과 누설전류 전도기구)

  • 정용국;임원택;손병근;이창효
    • Journal of the Korean Vacuum Society
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    • v.9 no.3
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    • pp.242-248
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    • 2000
  • BST thin films were prepared with various deposition conditions by rf-magnetron sputtering. As substrate temperature increases and Ar/$O_2$ratio decreases, the electrical properties of the BST films improve. The conventional Schottky model and modified-Schottky model were introduced in order to investigate the leakage-current-conduction mechanisms of the deposited films. It was found that the modified-Schottky model better describes the current-conduction mechanism in the BST films than the conventional Schottky model. From the modified-Schottky model, optical dielectric constant ($\varepsilon$), electronic drift mobility ($\mu$), and barrier height $({\phi}_b)are calculated as $\varepsilon$=4.9, $\mu$=0.019 $\textrm{cm}^2$/V-s, and ${\phi}_b=0.79 eV.

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Thickness effect on the ferroelectric properties of SBT thin films fabricated by LSMCD process (LSMCD공정으로 제조한 SBT 박막의 두께에 따른 강유전 특성)

  • 박주동;권용욱;연대중;오태성
    • Journal of the Korean Vacuum Society
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    • v.8 no.3A
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    • pp.231-237
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    • 1999
  • $SrBi_{22.4}Ta_2O_9$ (SBT) thin films of 70~150 nm thickness were prepared on platinized silicon substrates by Liquid Source Misted Chemical Deposition (LSMCD) process, and their microstructure, feroelectric and leakage current characteristics were investigated. By annealing at $800^{\circ}C$ for 1 hour in oxygen ambient, SBT films were fully crystallized to the Bi layered perovskite structure without preferred orientation. The grain size of the LSMCD- derived SBT films was about 100nm, and was not varied with the film thickness. $2P_r$ and $E_c$ of the SBT films increased with decreasing the film thickness, and the 70nm-thick SBT film exhibited $2P_r$ of 17.8 $\mu$C/$\textrm{cm}^2$ and $E_c$ of 74kV/cm at applied voltage of 5V. Within the film thickness range of 70~150nm, the relative dielectric permittivity of the LSMCD-derived SBT film decreased with decreasing the film thickness. Leakage current densities lower than $10^{-7}\textrm{A/cm}^2$ at 5V were observed in the SBT films thicker than 125nm.

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Channel Length에 따른 NMOSFET 소자의 Hot Carrier 열화 특성

  • Kim, Hyeon-Gi;Kim, Sang-Seop;Choe, Byeong-Deok
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.08a
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    • pp.240.1-240.1
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    • 2013
  • 본 연구에서는 Symmetric NMOSFET의 channel length에 따른 전기적 특성 분석에 관한 연구를 진행하였다. 특성 분석에 사용된 소자의 Gate oxide 두께는 6 nm 이며, 채널 Width/Length는 각각 10/10 ${\mu}m$, 10/0.2 ${\mu}m$ 이다. Drain Avalanche Hot Carrier(DAHC) 테스트를 진행하기 위하여 각각 스트레스 조건을 추출하였고, 조건에 해당되는 스트레스를 1700초 동안 인가하였다. 스트레스 후, Channel length가 10 ${\mu}m$과 0.2 ${\mu}m$인 두 소자의 특성을 측정, 분석결과 10 ${\mu}m$의 소자의 경우 문턱전압(VT)과 Subthreshold swing (SS)의 변화가 없었지만 0.2 ${\mu}m$의 소자의 경우 0.42V의 (from 0.67V to 1.09V) 문턱전압 변화 (VTH)와 71 mV/dec (from 79 mV/dec to 150 mV/dec))의 Swing (SS)변화를 보여 스트레스 후에 Interface trap이 증가하였음을 알 수 있다. off-state leakage current를 측정 결과 0.2 ${\mu}m$ 의 경우 leakage current의 양이 증가하였음을 알 수 있고 이는 드레인 부근에 증가된 interface trap에 의한 현상으로 판단된다. 상기 결과와 같이 DAHC 스트레스에 의한 소자의 열화 현상은 Channel length가 짧을수록 더 크게 의존하는 것을 확인하였다.

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Simple predictive heat leakage estimation of static non-vacuum insulated cryogenic vessel

  • Mzad, Hocine
    • Progress in Superconductivity and Cryogenics
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    • v.22 no.3
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    • pp.25-30
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    • 2020
  • The diminishing of heat leak into cryogenic vessels can prolong the storage time of cryogenic liquid. With the storage of cryogenic liquid reducing, the heat leak decreases, while the actual storage time increases. Regarding to the theoretical analysis, the obtained results seems to be constructive for the cryogenic insulation system applications. This study presents a predictive assessment of heat leak occurring in non-vacuum tanks with a single layer of insulation. A Radial steady-state heat transfer, based on heat conduction equation, is taken into consideration. Graphical results show the thermal performance of the insulation used, they also allow us to choose the appropriate insulation thickness according to the shape and diameter of the storage tank.

High resolution 5" full color field emission displays with new aging technique

  • Kim, J.M.;Hong, J.P.;Park, N.S.;Ryu, Y.S.;Jung, J.E.;Hong S.S.
    • Proceedings of the Korean Vacuum Society Conference
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    • 1998.02a
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    • pp.23-23
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    • 1998
  • High resolution field emission dispplay(FED) devices of 5 inch diagonal in size are fully developped for the applications of near-future flat ppanel dispplays. Under the unique gate-switching drive scheme electron trajectory pprofiles are simulated and tested by considering leakage effects of each ppixel. Uniquely-pprinted sppacer with high asppect ratio are fabricated on real ITO glass for high vacuum ppackaging. In addition new gas aging scheme of stabilizing field emitting array are extensively investigated during the sealing and exhausting pprocess in order to pprevent oxidation effects on the micro tipp. Finally fulll color images of 64 gray scale will be demonstrated.

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The Study on Dielectric and RTA Property of Oxide Thin-films (산화물 박막 커패시터의 RTA 처리와 유전 특성에 관한 연구)

  • Kim, I.S.;Lee, D.Y.;Cho, Y.R.;Song, J.S.
    • Proceedings of the KIEE Conference
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    • 2001.11a
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    • pp.23-25
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    • 2001
  • In this work, the $Ta_2O_5$ thin films were deposited on Pt/n-Si substrate by reactive magnetron sputtering and the RTA treatment at temperatures range from 650 to $750^{\circ}C$ in $O_2$ and vacuum. X-ray diffraction analysis, FE SEM, dielectric properties and leakage current density have been used to study the structural and electrical properties of the $Ta_2O_5$ thin films. XRD result showed that as- deposited films were amorphous and the annealed films crystallized (<$700^{\circ}C$) into ${\beta}-Ta_2O_5$. The crystallinity increased with temperature in terms of an increase in the intensity of the diffracted peaks(${\beta}-Ta_2O_5$) and annealing in oxygen reduced defect dang1ing Ta-O bonds. As deposited $Ta_2O_5$ films show the leakage current density $10^{-7}$ to $10^{-8}$ (A/$cm^2)$ at low electric fields (<200 kV/cm) However, it was found leakage current density of $Ta_2O_5$ thin films decreased with $O_2$ ambient annealing. The dielectric constant of the as deposited $Ta_2O_5$ thin films was ${\varepsilon}_r$ $9{\sim}11$ but the dielectric constant was increased after RTA treatment in $O_2$ ambient more then in vacuum.

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V-Based Self-Forming Layers as Cu Diffusion Barrier on Low-k Samples

  • Park, Jae-Hyeong;Mun, Dae-Yong;Han, Dong-Seok;Gang, Yu-Jin;Sin, So-Ra;Park, Jong-Wan
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.02a
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    • pp.409-409
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    • 2013
  • 최근, 집적 소자의 미세화에 따라 늘어난 배선 신호 지연 및 상호 간섭, 그리고 소비 전력의 증가는 초고집적 소자 성능 개선에 한계를 가져온다. 이에 따라 기존의 알루미늄(Al)/실리콘 절연 산화막은 구리(Cu)/저유전율 박막(low-k)으로 대체되고 있고, 이는 소자 성능 개선에 큰 영향을 미친다. 그러나 Cu는 Si과 low-k 내부로 확산이 빠르게 일어나 소자의 비저항을 높이고, 누설 전류를 일으키는 등 소자의 성능을 저하시킬 수 있는 문제점을 가지고 있다. 이러한 Cu의 확산을 막기 위하여 Ta, TaN 등과 같은 확산방지막에 대한 연구가 활발히 진행되어 왔으나, 배선 공정의 집적화와 low-k 대체에 따른 공정 및 신뢰성 문제로 인해 새로운 확산방지막의 개발이 필요하게 되었다. 이를 위해, 본 연구에서는 Cu-V 합금을 사용하여 low-k 기판 위에 확산방지막을 자가 형성 시키는 공정에 대한 연구를 진행하였다. 다양한 low-k 기판에서 열처리조건에 따른 Cu-V 합금의 특성을 확인하기 위해 4-point probe를 통한 비저항 평가와 XRD (X-ray diffraction) 분석이 이뤄졌다. 또한, TEM (transmission electron microscope)을 이용하여 $300^{\circ}C$에서 1 시간 동안 열처리를 거쳐 자가형성된 V-based interlayer가 low-k와 Cu의 계면에서 균일하게 형성된 것을 확인하였다. 형성된 V-based interlayer의 barrier 특성을 평가하고자 Cu-V합금/low-k/Si 구조와 Cu/low-k/Si 구조의 leakage current를 비교 분석하였다. Cu/low-k/Si 구조는 비교적 낮은 온도에서 leakage current가 급격히 증가하는 양상을 보였으나, Cu-V 합금/low-k/Si 구조는 $550^{\circ}C$의 thermal stress 에서도 leakage current의 변화가 거의 없었다. 이러한 결과를 바탕으로 열처리를 통해 자가형성된 V-based interlayer의 Cu/low-k 간 확산방지막으로서 가능성을 검증하였다.

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