• Title/Summary/Keyword: Vacuum electronics

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Wafer-Level Packaged MEMS Resonators with a Highly Vacuum-Sensitive Quality Factor

  • Kang, Seok Jin;Moon, Young Soon;Son, Won Ho;Choi, Sie Young
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.5
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    • pp.632-639
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    • 2014

  • Mechanical stress and the vacuum level are the two main factors dominating the quality factor of a resonator operated in the vacuum range 1 mTorr to 10 Torr. This means that if the quality factor of a resonator is very insensitive to the mechanical stress in the vacuum range, it is sensitive to mainly the ambient vacuum level. In this paper, a wafer-level packaged MEMS resonator with a highly vacuum-sensitive quality factor is presented. The proposed device is characterized by a package with out-of-plane symmetry and a suspending structure with only a single anchor. Out-of-plane symmetry helps prevent deformation of the packaged device due to thermal mismatch, and a single-clamped structure facilitates constraint-free displacement. As a result, the proposed device is very insensitive to mechanical stress and is sensitive to mainly the ambient vacuum level. The average quality factors of the devices packaged under pressures of 50, 100, and 200 mTorr were 4987, 3415, and 2127, respectively. The results demonstrated the high controllability of the quality factor by vacuum adjustment. The mechanical robustness of the quality factor was confirmed by comparing the quality factors before and after high-temperature storage. Furthermore, through more than 50 days of monitoring, the stability of the quality factor was also certified.

  • https://doi.org/10.5573/JSTS.2014.14.5.632 인용 PDF KSCI

The Characteristics Depending on the Annealing Conditions in the PDP Vacuum In-line Sealing

  • Kwon, Sang-Jik;Kim, Jee-Hoon;Jang, Chan-Kyu;Park, Sung-Hyun;Whang, Ki-Woong;Lee, Kyung-Wha
    • 한국정보디스플레이학회:학술대회논문집
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    • 2004.08a
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    • pp.703-706
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    • 2004

  • This paper deals with the various sealing conditions in a vacuum and the discharge characteristics. The MgO thin film is prepared by e-beam evaporation method. Sealing process was performed in a vacuum at panel temperature of 430 $^{\circ}C$. We find the cracks on the MgO film surface, which results in higher discharge voltage and lower luminous efficiency. The vacuum in-line sealing technology does not require additional annealing process but induces the MgO cracks because of the high temperature sealing cycle in a vacuum. Therefore we modify the vacuum in-line sealing cycle which the MgO cracks are not found and the good characteristics of plasma displays are found in higher sealing pressure at sealing temperature of 430 $^{\circ}C$.

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Electrical and Optical Characterization of the Vacuum In-Line Sealed PDP Panel

  • Kwon, Sang-Jik;Kim, Jee-Hoon;Kim, Tae-Ho;Shon, Byeong-Kyoo;Yang, Hwi-Chan
    • 한국정보디스플레이학회:학술대회논문집
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    • 2003.07a
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    • pp.832-835
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    • 2003

  • By using vacuum in-line driving and photoluminescence measuring method, we have observed the electrical and optical characteristics of the vacuum in-line sealing technology and analyzed the effect of the base vacuum level before filling the plasma gas. In the case of base vacuum level of $1{\times}10^{-3}$torr, the firing voltage of a 2-inch diagonal PDP panel was ranged from 310 to 345V depending on the plasma gas pressure of 200 to 300torr and luminous efficiency was ranged from 0.0227 to 0.0367 lm/W depending on the input voltage level of 330 to 225V. While, in the case of $1{\times}10^{-6}$, the characteristics were significantly improved. As a results, the firing voltage was ranged from 295 to 318V and luminous efficiency was from 0.0278 to 0.0451 lm/W.

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Device Optimization for Suppression of Short-Channel Effects in Bulk FinFET with Vacuum Gate Spacer (진공 게이트 스페이서를 지니는 Bulk FinFET의 단채널효과 억제를 위한 소자구조 최적화 연구)

  • Yeon, Ji-Yeong;Lee, Khwang-Sun;Yoon, Sung-Su;Yeon, Ju-Won;Bae, Hagyoul;Park, Jun-Young
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.35 no.6
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    • pp.576-580
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    • 2022

  • Semiconductor devices have evolved from 2D planar FETs to 3D bulk FinFETs, with aggressive device scaling. Bulk FinFETs make it possible to suppress short-channel effects. In addition, the use of low-k dielectric materials as a vacuum gate spacer have been suggested to improve the AC characteristics of the bulk FinFET. However, although the vacuum gate spacer is effective, correlation between the vacuum gate spacer and the short-channel-effects have not yet been compared or discussed. Using a 3D TCAD simulator, this paper demonstrates how to optimize bulk FinFETs including a vacuum gate spacer and to suppress short-channel effects.

  • https://doi.org/10.4313/JKEM.2022.35.6.6 인용 PDF KSCI