• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.672-675
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• 1997

This paper proposes a structure of the control system for the step & scan exposure tool. The step & scan exposure tool is used for the manufacturing process of the semiconductor DRAM memory of giga bit. The control system employs the VME bus instead of the conventional ISA bus so that all control signals and data can be managed separately by the 4 VME-PCs for fast and fault-free flow of signals for multi-tasking. A high speed I/O card is equipped for the real-time monitoring and control of the sub module equipment. Then all the subsystems are integrated and aligned for the operation of the step & scan exposure tool with the VME bus and, I/O card.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1111-1115
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• 1987

This paper describes of VME-BSA which is a tool for the development, mainternance and repair. In micro/mini computer system using VMEbus as a backplane bus, VME-BSA has some good facilities such as acquiring, storing and analyzering the information (address, data, etc.) on VMEbus according to the various condition which is set by users, and therefore it is easy to isolate and find many complete errors on bus.

• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2914-2922
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• 1997

For FA (factory automation) and ATE (automatic test equipment) in the industrial area, the standard bus needs to increase the system performance of multiprocessor environment. VME(versa module european package format) bus is appropriated to the standard bus but has features of small package and low board density. Beside, the density of board and semiconductor have grown to become significant issues that affect development time, project cost and field diagnostics. To fit this trend, in this paper, we composed Revision C.1 (IEEE std. P1014-1987) of the integrated environment for the main function such as arbitration, interrupt and interface between, VMEbus and several control modules Also the designed, VME system controller is implemented on FPGA that can be located even into slot 1. The control and function modules are coded with VHDL mid-fixed description method and then those operations are verified by simulation. As a result of experiment, we confirmed the most important that is the operation of Bus timer about Bus error signal should occur within $56{\mu}m$, and both control and function modules have the reciprocal operation correctly. Thus, the constructed VHDL library will be able to apply the system based VMEbus and ASIC design.

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2324-2326
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• 1998

Plant controller using VME bus is developed. This controller is a PLC designed to control up to 768 I/O units of POSFA PLC which has been developed already by POSCON. In many programming aspects, it adopts IEC 1131, international standard of PLC programming to keep up with international trends. A system software and a controller architecture including CPU board, DSP board and bus extension board are developed to support the IEC 1131, and becomes a base of E.I. controller being developed now.

• Proceedings of the KIEE Conference
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• 1990.11a
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• pp.439-442
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• 1990

A powerful general purpose image processing processor is developed using a high-speed DSP chip, TMS320C30. The image processing processor, compatible to the standard VME bus, is composed of VME bus interface unit, video rate image grabbing/coding unit, TMS320C30 interface unit and bank of high-speed SRAMs. The performance is evaluated experimentally with the general image processing algorithms and the results show that the developed processor is capable of high speed image processing.

• Journal of the Korea Society of Computer and Information
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• v.22 no.7
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• pp.9-16
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• 2017

In this paper, we propose a development method of portable Automatic Test Equipment based on PXIe platform. Legacy VME form factor structured test equipment has limited reuse and expansion of modules due to unapplied bus specification. In particular, these limitations can cause development periods and costs to increase, and the reliability of environmental conditions is lacking due to non-standard modules. The test equipment of the proposed PXIe platform can use diverse COTS modules to shorten the development period and minimize the instability between developments. The PXIe development module works with standard Xilinx FPGAs, PXIe Windows device drivers, and applications on standard PXIe buses. The use of standard bus and COTS modules increases scalability and reusability, enabling rapid development and excellent maintenance. Through the test, we show the proposed test equipments can be implemented efficiently between the development processes and proved their reliability through function tests and environmental tests.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.2
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• pp.109-114
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• 2008

In this paper, a dynamic learning controller for robot manipulator is implemented using real-time operating system with capabilities of multitasking, intertask communication and synchronization, event-driven, priority-driven scheduling, real-time clock control, etc. The controller hardware system with VME bus and related devices is developed and applied to implement a dynamic learning control scheme for robot manipulator. Real-time performance of the proposed dynamic learning controller is tested and evaluated for tracking of the desired trajectory and compared with the conventional servo controller.

• 제어로봇시스템학회:학술대회논문집
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• 1992.10a
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• pp.387-392
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• 1992

This paper presents a local trajectory generation method which is based on a sequence of reference posture-velocities and the efficient low level control algorithm which constructs the complete smooth curve from the trajectory specification. The reference trajectory generator(RTG) which is in between the local path planner(LPP) and the robot motion controller(RMC) generates a sequence of set-points for each path segments from the LPP and pass it to the RMC. The RMC controls the motions of vehicle which should follow the sequence. In the feedback controller of VMC, the method which compensates robot posture-velocity error correctly is used. These methods are implemented on indoor autonomous vehicle, 'ALIVE' mobile robot. The ALIVE mobile robot system is implemented on the 32bit VME bus system: the two VME CPU's are used for RTG and RMC, while the 80C196KC-based VME board is used for motor controller.

• Journal of the Korean Society for Precision Engineering
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• v.10 no.4
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• pp.227-235
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• 1993

In this paper, the development of a high performance flexible controller is described. The hardware of the controller, based on VME-bus, consists of four M68020 single-board computers (32-bit) with M68881 numerical coprocessors, two M68040 single board donputers, I/O devices (such as A/D and D/A converters, paraller I/O, encoder counters), and bus-to-bus adaptor. This software, written in C and based on X-window environment with Unix operating system, includes : text editor, compiler, downloader, and plotter running in a host computer for developing control program ; device drivers, scheduler, and mathemetical routines for the real time control purpose ; message passing, file server, source level debugger virtural terminal, etc. The hardware and software are structured so that the controller might have both flexibility and extensibility. In papallel to the controller, a three degrees of freedom kinematically redundant robot has been developed at the same time. The development of the same time. The development of the robot was undertaken in order to provide, on the one hand, a computationally intensive plant to which to apply the controller, and on the other hand a research tool in the field of kinematically redundant manipulator, which is, as such, an important area. By using the controller, dynamic control of the redundant manipulator was successfully experimented, showing the effectiveness and flexibility of the controller.

• Journal of Sensor Science and Technology
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• v.7 no.2
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• pp.124-130
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• 1998

High-speed 3D vision systems are essential for autonomous robot or vehicle control applications. In our study, a stereo vision process has been developed. It consists of three steps : extraction of edges in right and left images, matching corresponding edges and calculation of the 3D map. This process is implemented in a VME 150/40 Imaging Technology vision system. It is a modular system composed by a display, an acquisition, a four Mbytes image frame memory, and three computational cards. Programmable accelerator computational modules are running at 40 MHz and are based on TMS320C31 DSP with a $64{\times}32$ bit instruction cache and two $1024{\times}32$ bit internal RAMs. Each is equipped with 512 Kbytes static RAM, 4 Mbytes image memory, 1 Mbytes flash EEPROM and a serial port. Data transfers and communications between modules are provided by three 8 bit global video bus, and three local configurable pipeline 8 bit video bus. The VME bus is dedicated to system management. Tasks between DSPs are distributed as follows: two DSPs are used to edges detection, one for the right image and the other for the left one. The last processor computes the matching process and the 3D calculation. With $512{\times}512$ pixels images, this sensor generates dense 3D maps at a rate of about 1 Hz depending of the scene complexity. Results can surely be improved by using a special suited multiprocessors cards.