• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.3
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• pp.23-32
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• 2007

The H.264/AVC video coding standard uses rate distortion optimization (RDO) method to improve the compression performance in the intra prediction. The complexity and computational load are increased more than previous standard by using this method, even though this standard selects the best coding mode for the current macroblock. This paper proposes a fast intra mode decision algorithm for H.264/AVC encoder based on dominant edge direction (DED). To apply the idea, this algorithm uses the approximation of discrete cosine transform (DCT) coefficient. By detecting the DED, 3 modes instead of 9 modes are chosen for RDO calculation to decide the best mode in the $4{\times}4$ luma block. As for the $16{\times}16$ luma and $8{\times}8$ chroma block, instead of 4 modes, only 2 modes are searched. Experimental results show that the computation time of the proposed algorithm is decreased to about 72% of the full search method with negligible quality loss.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.1
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• pp.1-9
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• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into a H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel for the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks. The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit or a field synchronized with the A/D converter. The implemented H/W used the 54％(12943) LAB(Logic Array Block) and 9％(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation. that is. processing 60 fields/sec(30 frames/sec).

• Journal of Broadcast Engineering
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• v.17 no.2
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• pp.422-425
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• 2012

This paper proposes the CU-based approach for merge candidate list construction for providing reduced complexity and improved parallelism compared to the PU-based one. In the proposed method, a CU can have only one merge candidate list. So, Only one common merge candidate list is used for all PUs in a CU regardless of the PU partition type. The simulation results of proposed method showed that the encoder computational complexity was decreased by 3% to 6% and the decoder computational complexity was negligible change with the penalty of roughly 0.2% - 0.5% coding loss. The proposed method has several advantages: it provides simpler design, reduced complexity, and improved parallelism.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3C
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• pp.271-278
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• 2006

Rate-constrained coding is one of the many coding-efficiency oriented tools of H.264/AVC, but mode decision process of RDO(Rate distortion optimization) requires high computational complexity. Many fast mode decision algorithms have been proposed to reduce the computational complexity of mode decision. In this paper, we propose two algorithms for reduction of mode decision in H.264/AVC, which are the fast reference frame selection and selective intra prediction mode decision. Fast reference frame selection is efficient for inter predication and selective intra prediction mode decision can effectively reduce excessive calculation load of intra prediction mode decision. The simulation results showed that the proposed methods could reduce the encoding time of the overall sequences by 44.63% on average without any noticeable degradation of the coding efficiency.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.4
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• pp.275-285
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• 2003

The now video coding standard H.264 employs variable block size motion compensation, multiple references, and quarter-pel motion vector accuracy. These techniques are key features to accomplish higher coding gain, however, at the same time main factors that increase overall computational complexity. Therefore, in order to apply H.264 to many applications, key techniques are requested to improve their speed. For this reason, we propose a fast motion estimation which is suited for variable block size motion communication. In addition, we propose a fast mode decision method to choose the best mode at early stage. Experimental results show the reduction of the number of SAT SATD calculations by a factor of 4.5 and 2.6 times respectively, when we compare the proposed fast motion estimation and the conventional MVFAS $T^{［8-10］}$. Besides, the number of RDcost computations is reduced by about 45%. Therefore, the proposed methods reduces significantly its computational complexity without noticeable coding loss.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.3 s.309
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• pp.92-99
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• 2006

In this paper, a low-power deblocking filter structure for H.264 video coding algorithm is proposed. By sharing addition hardware for common filter coefficients, we have designed an efficient deblocking filter structure. Proposed deblocking filter utilizes MUX and DEMUX circuits for input data sharing and shows 44.2% reduction for add operation. In the HDL coding simulation and FPGA implementation, we achieved 19.5% and 19.4% gate count reduction, respectively, comparison with the conventional deblocking filter structure. Due to its efficient processing scheme, the proposed structure can be widely used in H.264 encoding and decoding SoC.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.8C
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• pp.793-800
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• 2005

Computation of multimedia data increases in portable devices with the advances of the mobile and personal communication services. The energy management of such devices is very important for the battery-powered operation hours. The motion estimation in a video encoder requires huge amount of computation, and hence, consumes the largest portion of the energy consumption. In this paper, we propose a novel architecture that a low energy management scheme can be applied with several fast-search algorithms. The energy-constrained Vdd hopping (ECVH) technique reduces power consumption of the motion estimation by adaptively changing the search algorithm, the operating frequency, and the supply voltage using the remaining slack time within given power-budget. We show that the ECVH can be applied to the architecture, and that the power consumption can be efficiently reduced.

• Journal of Broadcast Engineering
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• v.17 no.6
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• pp.1029-1039
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• 2012

In this papar, we propose a new motion estimation and coding technique using adaptive motion vector resolution. Currently, HEVC encodes a video using 1/4 motion vector resolution. If there are high texture regions in a picture, HEVC can't get a performance enough. So, we insert additional 1-bit flag meaning whether motion vector resolution is 1/4 or 1/8 in PU syntax. Therefore, decoder can recognize the transmitted motion vector resolution. Experimental results show that maximum coding efficiency gain of the proposed method is up to 5.3% in luminance and 7.9% in chrominance. Average computional time complexity is increased about 33% in encoder and up to 5% in decoder.

• Journal of Broadcast Engineering
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• v.19 no.3
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• pp.405-414
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• 2014

High Efficiency Video Coding(HEVC) obtains high compression ratio by applying recursive quad-tree structured coding unit(CU). However, this recursive quad-tree structure brings very high computational complexity to HEVC encoder. In this paper, we present fast CU decision algorithm in recursive quad-tree structure. The proposed algorithm estimates initial CU size before CTU encoding and checks the proposed condition using Coded Block Flag(CBF) and Rate-distortion cost to achieve the fast encoding time saving. And, intra mode estimation is also possible to be skipped using the CBF values acquired during the inter PU mode estimations. Experiment results shows that the proposed algorithm saved about 49.91% and 37.97% of encoding time according to the weighting condition.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.3
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• pp.63-69
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• 2017

In next generation satellite broadcasting system, requirement of high throughput efficiency has been increasing continuously. To increase throughput efficiency and improve bit error performance simultaneously, FTN method and LDPC codes are employed in new sattelite standard, DVB-S3 system. This paper considered three kinds of methods for increase throughput efficiency. Firstly, as conventional one, high coding rate parity matrix in LDPC encoder is considered. Secondly, punctured coding scheme which delete the coded symbols according to appropriate rules is considered. Lastly, FTN method which transmit fater than Nyquist rate is considered. Among of three kinds of methods, FTN method is most efficient in aspect to performance while maintain same throughput efficiency.