• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.187-187
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• 2004

In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF($2^8$) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.29-38
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• 2004

In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF(2$^{8}$ ) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3C
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• pp.398-407
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• 2004

In this paper, a blind watermarking method which is suitable to the video compression using 2-D discrete wavelet transform was proposed and implemented into the hardware using VHDL(VHSIC Hardware Description Language). The goal of the proposed watermarking algorithm is the authentication about the manipulation of the watermark embedded image and the detection of the error positions. Considering the compressed video image, the proposed watermarking scheme is unrelated to the quantization and is able to concurrently embed or extract the watermark. We experimentally verified that the lowest frequency subband(LL4) is not sensitive to the change in the spatial domain, so LL4 subband was selected for the mark space. And the combination of the bitplanes which has the properties of both the minimum degradation of the image and the robustness was chosen as the embedded Point in the mark space in LL4 subband. Since we know the watermark embedded positions and the watermark is embedded by not varying the value but changing the value, the watermark can be extracted without the original image. Also, for the security when exposing the watermark embedded position, we embed the encrypted watermark by the block cipher. The proposed watermark algorithm shows the robustness against the general image manipulation and is easily transplanted into the image or video compressor with the minimal changing in the structure. The designed hardware has 4037 LABs(24％) and 85 ESBs(3％) in APEX20KC EP20K400CF672C7 FPGA of Altera and stably operates in 82MHz clock frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.4C
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• pp.365-373
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• 2003

In this paper, we design a versatle RS decoder which can decode RS codes of any block length n as well as any message length k, based on a modified Euclid's algorithm (MEA). This unique feature is favorable for a shortened RS code of any block length it eliminates the need to insert zeros before decoding a shortened RS code. Furthermore, the value of error correcting capability t can be changed in real time at every codeword block. Thus, when a return channel is available, the error correcting capability can be adaptiverly altered according to channel state. The decoder permits 4-step pipelined processing : (1) syndrome calculation (2) MEA block (3) error magnitude calculation (4) decoder failure check. Each step is designed to form a structure suitable for decoding a RS code with varying block length. A new architecture is proposed for a MEA block in step (2) and an architecture of outputting in reversed order is employed for a polynomial evaluation in step (3). To maintain to throughput rate with less circuitry, the MEA block uses not only a multiplexing and recursive technique but also an overclocking technique. The adaptive RS decoder over GF($2^8$) with the maximal error correcting capability of 10 has been designed in VHDL, and successfully synthesized in a FPGA.

• Convergence Security Journal
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• v.12 no.4
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• pp.17-23
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• 2012

Recently, the research for cryptographic algorithm, in particular, a stream cipher has been actively conducted for wireless devices as growing use of wireless devices such as smartphone and tablet. LFSR based random number generator is widely used in stream cipher since it has simple architecture and it operates very fast. However, the conventional multi-LFSR RNG (random number generator) suffers from its hardware complexity as well as very closed correlation between the numbers generated. A leap-ahead LFSR was presented to solve these problems. However, it has another disadvantage that the maximum period of the generated random numbers are significantly decreased according to the relationship between the number of the stages of the LFSR and the number of the output bits of the RNG. This paper presents new leap-ahead LFSR architecture to prevent this decrease in the maximum period by applying segmentation technique to the conventional leap-ahead LFSR. The proposed architecture is implemented using VHDL and it is simulated in FPGA using Xilinx ISE 10.1, with a device Virtex 4, XC4VLX15. From the simulation results, the proposed architecture has only 20% hardware complexity but it can increases the maximum period of the generated random numbers by 40% compared to the conventional Leap-ahead archtecture.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.3
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• pp.8-16
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• 1999

This paper describes a VLSI design of Reed-Solomon(RS) decoder using the modified Euclid algorithm, with the main theme focused on the $\textit{GF}(2^8)$. To get area-efficient design, a number of new architectures have been devised with maximal register and Euclidean ALU unit sharing. One ALU is shared to replace 18 ALUs which computes an error locator polynomial and an error evaluation polynomial. Also, 18 registers are shared to replace 24 registers which stores coefficients of those polynomials. The validity and efficiency of the proposed architecture have been verified by simulation and by FLEX$^TM$ FPGA implementation in hardware description language VHDL. The proposed Reed-Solomon decoder, which has the capability of decoding RS(208,192,17) and RS(182,172,11) for Digital Versatile Disc(DVD), has been designed by using O.6$\mu\textrm{m}$ CMOS TLM Compass$^TM$ technology library, which contains totally 17k gates with a core area of 2.299$\times$2.284 (5.25$\textrm{mm}^2$). The chip can run at 20MHz while the DVD requirement is 3.74MHz.

• Convergence Security Journal
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• v.7 no.2
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• pp.17-25
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• 2007

In this paper, an algorithm that provisions proportional differentiation of packet delays is proposed with an objective for enhancing quality of service (QoS) in future packet networks. It features an adaptive scheme that adjusts the target delay every time slot to compensate the deviation from the target delay which is caused by the prediction error on the traffic to be arrived in the next time slot. It predicts the traffic to be arrived at the beginning of a time slot and measures the actual arrived traffic at the end of the time slot. The difference between them is utilized to the delay control operation for the next time slot to offset it. As it compensates the prediction error continuously, it shows superior adaptability to the bursty traffic as well as the exponential rate traffic. It is demonstrated through simulations that the algorithm meets the quantitative delay bounds and shows superiority to the traffic fluctuation in comparison with the conventional non-adaptive mechanism. The algorithm is implemented with VHDL on a Xilinx Spartan XC3S1500 FPGA and the performance is verified under the test board based on the XPC860P CPU.

• Journal of the Semiconductor & Display Technology
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• v.10 no.4
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• pp.7-13
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• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6C
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• pp.625-631
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• 2002

This paper presents a MSB-first digit-serial systolic array for computing modular multiplication of A(x)B(x) mod G(x) in finite fields $GF(2^m)$. From the MSB-first multiplication algorithm in $GF(2^m)$, we obtain a new data dependence graph and design an efficient digit-serial systolic multiplier. For circuit synthesis, we obtain VHDL code for multiplier, If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has much more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of unidirectional data flow and regularity, it shows good extension characteristics with respect to m and L.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.527-533
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• 2008

Motion compensation always produces the principal bottleneck in the real-time high quality video applications. Therefore, a fast dedicated hardware is needed to perform motion compensation in the real-time video applications. In many video encoding methods, the frames are partitioned into blocks of Pixels. In general, motion compensation predicts present block by estimating the motion from previous frame. In motion compensation, the higher pixel accuracy shows the better performance but the computing complexity is increased. In this paper, we studied an architecture of motion compensator suitable for H.264/AVC encoder that supports quarter-pixel accuracy. The designed motion compensator increases the throughput using transpose array and 3 6-tap Luma filters and efficiently reduces the memory access. The motion compensator is described in VHDL and synthesized in Xilinx ISE and verified using Modelsim_6.1i. Our motion compensator uses 36-tap filters only and performs in 640 clock-cycle per macro block. The motion compensator proposed in this paper is suitable to the areas that require the real-time video processing.