• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.455-456
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• 2007

Nowaday it is main issues for us to protect from the polluted water which is flowing in streams and rivers simultaneously. This paper proposed a water maintenance control system using pH sensor. Also the work enables water analysis downloading VHDL coding to FPGA through Max+plus II simulation tool for display realization.

• Proceedings of the Korea Information Processing Society Conference
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• 2003.05a
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• pp.23-26
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• 2003

본 논문은 웨이블릿 변환 과정을 통해서 분해한 영상을 Shapiro가 제안한 효율적인 영상 압축 방법인 EZW(Embedded Zerotree Wavelet)알고리즘을 하드웨어로 설계하였다. 이를 위한 하드웨어 구조를 제시하고 VHDL로 모델링 하여 FPGA를 통해 검증하였다.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10b
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• pp.658-660
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• 2003

본 논문에서는 AMBA 기반의 FPD 시스템에 적용 가능한 콘트라스트 컨트롤러를 설계 및 구현하였다. 제안한 콘트라스트 컨트롤러 내부에는 AMBA의 인터페이스 spec을 준수한 AMBA AHB 컨트롤러와 콘트라스트조정 블록, 메모리 컨트롤러. FPD 컨트롤러가 내장되어있다. 구현한 알고리즘은 실시간 처리가 가능하며 콘트라스트의 범위를 조정하는 가중치를 가진 알고리즘으로 기준되는 값을 이용하여 콘트라스트의 효율적인 조정이 가능하다. 콘트라스트 컨트롤러는 VHDL로 설계하였으며 FPGA를 이용한 H/W를 구현하여 TFT-LCD panel에 디스플레이 하여 검증하였다.

• Journal of Power Electronics
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• v.16 no.2
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• pp.553-563
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• 2016

This paper presents a digital hardware implementation of a real-time simulator for a multiphase drive using a field-programmable gate array (FPGA) device. The simulator was developed with a modular and hierarchical design using very high-speed integrated circuit hardware description language (VHDL). Hence, this simulator is flexible and portable. A state-space representation model suitable for FPGA implementations was proposed for a dual three-phase induction machine (DTPIM). The simulator also models a two-level 12-pulse insulated-gate bipolar transistor (IGBT)-based voltage-source converter (VSC), a pulse-width modulation scheme, and a measurement system. Real-time simulation outputs (stator currents and rotor speed) were validated under steady-state and transient conditions using as reference an experimental test bench based on a DTPIM with 15 kW-rated power. The accuracy of the proposed digital hardware implementation was evaluated according to the simulation and experimental results. Finally, statistical performance parameters were provided to analyze the efficiency of the proposed DTPIM hardware implementation method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.307-310
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• 2001

In this paper we describe the design and implementation of uplink receiver for BWLL base station modem. The demodulator consists of digital down converter, matched filter and synchronization circuits. For symbol timing recovery we use Gardner algorithm. And we use forth power method and decision directed method for carrier frequency recovery and phase recovery, respectively. For the sake of performance analysis, we compare simulation results with the board implemented by FPGA which is APEX20KE series chip for Alter. The performance results show it works quite well up to the condition that a frequency offset equal to 4.7% of symbol rate.1

• Journal of rehabilitation welfare engineering & assistive technology
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• v.10 no.3
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• pp.237-242
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• 2016

The major advantage of slip-ring technology in Spiral CT is that it facilitates continuous rotation of the x-ray tube, so that volume data can be acquired from a patient quickly. Not only for such a fast scan, but also for the dose reduction purpose, high signal-to-noise ratio and fast data acquisition system is required. In this study, we have built a multi-channel photodetector and multi-channel data acquisition system for CT application. The detector module consisted of CdWO4 crystal and Si photodiode in 16 channels. For the performance test of the preamplifier stage, both the transimpedance and switched integrator types are optimized for the photodetector modules. Switched integrator showed better noise performance in the limited bandwidth which is suitable for the current CT application. The control sequence for data acquisition and 20 bit ADC is designed with VHDL(Very High Speed Integrated Circuit Hardware Description Language) and implemented on FPGA(Field Programmable Gate Array) chip. Our Si photodiode detector module coupled to CdWO4 crystal showed comparable signal with other commercially available photodiode for CT. Switched integrator type showed higher SNR but narrower bandwidth compared to transimpedance preamplifier. Digital hardware is designed by FPGA, so that the control signal could be redesigned without hardware alteration.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.37 no.3
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• pp.45-55
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• 2000

In this paper, we proposed the hardware architecture of wavelet transform digital filter for an image processing. Filter bank pyramid algorithm is used for wavelet transform and each fillet is implemented by the FIR filter. For DWT computation, because the memory controller is implemented by hardware, we can efficiently process the multisolution decomposition of the image data only input the parameter. As a result of the image Processing in this paper, 33㏈ PSNR has been obtained on 512$\times$512 B/W image due to 11-bit mantissa processing in FPGA Implementation. And because of using QMF( Quadrature Mirror Filter) properties, it reduces half number of the multiplier needed DWT(Discrete Wavelet Transform) computation so the hardware size is reduced largely. The proposed scheme can increase the efficiency of an image Processing as well as hardware size reduced. The hardware design proposed of DWT fillet bank is synthesized by VHDL coding and then the test board is manufactured, the operating Program and the application Program are implemented using MFC++ and C++ language each other.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.1 no.1
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• pp.21-33
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• 1997

This dissertation deals with the design and VLSI implementation of the MTP(Multimedia Transport Protocol) protocol for the high speed networks. High throughput, functional diversity and flexible adaptation are key requirements for the future transport protocol. However it is very difficult to satisfy all these requirements simultaneously. Fortunately, the future networks will be very reliable. It means that the future transport protocol will usually perform some fixed functions without the protocol state information. According to this concept, we proposed and designed the MTP protocol that is consisted of Information Plane and Control Plane. Information Plane performs some fixed functions that are independent of the protocol state information as far as no error. However Control Plane manages the protocol state information and controls the operation of Information Plane. Our MTP protocol was finally implemented as an FPGA chip using the VHDL. We built a testbed for verification of the implemented protocol, and it was shown that the MTP protocol worked correctly and made a throughput of about 800 Mbps. Our future works include the addition of multiplexing and multicasting capabilities to our protocol for multimedia applications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.1
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• pp.109-114
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• 2010

In this paper, the implementation of a human signal sensing module that has capabilities to check and restore the weak signals from the human body is presented. A module presented in this paper consists of processing and sensing elements related to human pulse and body temperature and a controller implemented with SoC design method. PPG data is detected by a noise filtering process toward the amplified signal which is from the operating frequency between 0.1Hz - 10Hz. A digital temperature sensor is used to check the body temperature. A sensor outputs the corresponding value of the electric voltage according to the body temperature. Moreover, this paper discusses the implementation of an enhanced microprocessor which is synthesized with VHDL as a part of the SoC development and used to control the entire module. The SoC processor is implemented on a Xilinx Spartan 3 XC3S1000 device and has the achieved operating frequency of 10MHz. The implemented SoC processor core is successfully tested with macro memories in FPGA and the experimental results are hereby shown.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1C
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• pp.69-77
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• 2002

Sine digital signal processing for motion pictures requires huge amount of data computation to store, manipulate and transmit, more effective data compression is necessary. Therefore, the ITU-T recommended H.26x as data compression standards for digital motion pictures. The data compression method that eliminates time redundancies by motion estimation using relationship between picture frames has been widely used. Most video conding systems employ block matching algorithm for the motion estimation and compensation, and the algorithm is based on the minimun value of cast functions. Therefore, fast search algorithm rather than full search algorithm is more effective in real time low data rates encodings such as H.26x. In this paper, motion estimation employing the Nearest-Neighbors algorithm is designed to reduce search time using FPGA, coded in VHDL, and simulated and verified using Xilink Foundation.