• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2534-2536
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• 2002

This paper presents the design of high speed bit and word processor for sequence logic control using a FPGA. This FPGA is able to execute sequence instruction during program fetch cycle, because the program memory was separated from the data memory for high speed execution at 40MHz clock. Also this processor has 274 instructions set with a 32bit fixed width, so instruction decoding time and data memory interface time was reduced. This FPGA was synthesized by V600EHQ240 and Foundation tool of Xilinx company. The final simulation was successfully performed under Foundation tool simulation environment. And the FPGA programmed by VHDL for a 240 pin HQFP package. Finally the benchmark was performed to prove that the designed for bit and word processor has better performance than Q4A of Mitsubishi for the sequence logic control.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.254-256
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• 2005

This paper describes a design of a vector control module for AC motor using high density FPGA. In the proposed vector controller, the vector control blocks including inverse dq transform, space vector PWM and quadrature encoder pulse module are implemented in a FPGA using a VHDL. The simulation results are provided to show the validity of the proposed vector control module.

• Proceedings of the KSR Conference
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• 2000.05a
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• pp.336-343
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• 2000

This paper proposes the failsafe control logic. which has applied to the voting on the TMR system by using FPGA The self-detection circuit is also designed for detecting a characteristic of fault at TMR system. The fault producing in the self-detection system is largely classified among an intermittent fault, a transient fault and a permanent fault. If it is happened to the permanent fault, the system can be failed. Therefore, it is designed the logic circuit which is not transferred the permanent fault to the system after shut off output. The control logic of the Fail Safe proposed in the paper is required for a circuit integrate of device to minimize the failure happened. Therefore, it makes to design FPGA with modeling of VHDL. The circuit of the Fail Safe of TMR system is able to apply to nuclear system, rail-way system, aerospace and aircraft system which is required for high reliability.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.3
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• pp.304-312
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• 1999

In order to make industrial robots and CNC machine tools perform tasks efficiently, each axis has to be accelearated and decelerated appropriately. The existing techniques for the acceleration and deceleration of industrial robots and CNC machine tools are not efficient to generate velocity profiles. Thus, these previous techniques cannot generate velocity generating velocity profiles that cannot be generated by them. Based on the proposed approach, an acceleration and deceleration circuit for industrial robots and CNC machine tools is designed with a FPGA by using the VHDL.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.652-654
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• 2016

This paper shows the Design and implementation of sinusoidal BLDC motor drive logic using SVPWM method with FPGA. Sinusoidal BLDC motor driver logic consists of sine-wave PWM generator, dead-time and lead angle control logic. PWM generator logic is designed using SVPWM method for increase of 15.5% linear domain than general sine-wave PWM. This logic is verified and implemented using Spartan-6 FPGA Board. Test results show that THD(Total Harmonic Distortion) of motor-driving current is 19.2% and rotor position resolution is 1.6 degree.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1113-1124
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• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel fur the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit of a field synchronized with the A/D converter. The implemented H/W used the 69%(16980) LAB(Logic Array Block) and 9%(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation of 60 fields/sec(30 frames/sec).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.69-73
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• 2006

일반신호기는 정해진 신호시간에 따라 독립적으로 운영되는 정주기신호기와 TOD(Time of Day)식 신호기이다. 이런 일반신호기의 단점으로는 변동되는 교통량에 대응이 불가능하고, 교통량에 관계없이 연속적으로 신호체계가 이루어지기 때문에 차량의 이동성이 비효율적으로 됨에 따라 생산성 감소, 에너지낭비 및 자동차 배기가스 증가를 초래하고 있다 이를 개선하기 위한 방법으로서 본 논문에서는 4차선의 주차로와 2차선의 소방로로 이루어진 교차로에서 주차로의 교통량이 많을 경우, 차로에서는 녹색불이 지속되어 교통의 흐름을 원활하게 해주며, 소방로에서 차량이 일정량 증가하게 되면, 주차로의 신호등이 적색등을 바꾸어 소방로의 차량이 교통되도록 하는 지능형 교통체계에 대해 VHDL을 이용하여 지능형 신호체계 시스템을 설계하였다.

• Proceedings of the KIEE Conference
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• 2000.11b
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• pp.336-338
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• 2000

Recently many studies have been performed for variable speed control of induction motor. Direct Torque Control(DTC) is emerging technique for variable speed control of PWM inverter driven induction motor. DTC allows the direct control of stator flux and instantaneous torque through simple algorithm. In this paper ASIC design technique using VHDL is applied to DTC based speed control of induction motor. ASIC for DTC based speed control is designed through the description of coordinate transformation, speed controller stator flux and torque estimator, stator flux and torque controller, stator flux position detector. FSM(Finite State Machine) and inverter voltage switching vector. Finally the above system has been implemented on the FPGA (XC4052XL-PG411). Simulation and experiment has been performed to verify the performance of the designed ASTC.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.669-673
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• 2004

인터넷의 사용이 증가, 네트워크 기술이 발달하면서 컴퓨터 및 하드웨어 장비는 고속화 대용량화, 소형화 추세로 가고 있고, 기존에 외부 인터페이스와의 데이터 송수신 또한 병렬 포트를 이용한 통신이 많았으나, 외부 장비의 소형화와 고속화 그리고 휴대화가 요구되면서 차츰 직렬 포트를 이용하여 적은 전송라인을 이용한 외부 장비와의 인터페이스가 요구 되게 되었다. 본 논문에서는 내부 모듈간의 인터페이스와 외부 장치와의 데이터 송/수신이 가능한 UART 인터페이스 모듈을 하드웨어 설계언어인 VHDL 언어를 이용하여 설계하였으며, FPGA 칩인 Xilinx(Spartan II) 데스트 보드에 다운로드하여 시뮬레이션 하였다. 또한 양방향성 공통 버스로의 인터페이스 회로 설계와 다른 클럭으로 동작하는 시스템과의 비동기 회로의 동작 메커니즘을 쉽게 설계하였고, 비동기 통신 기능에 있어서 실제로 사용이 가능하도록 설계하였다.