• Journal of Korean Electronics
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• v.17 no.10
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• pp.72-79
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• 1997

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.281-284
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• 2008

This paper describes ASIC design of multimedia SoC Platform. The implemented Platform consists of 32-bit OpenRISC1200 Microprocessor, WISHBONE on-chip bus, VGA Controller, Debug Interface, SRAM Interface and UART. The 32-bit OpenRISC1200 processor has 5 stage pipeline and Harvard architecture with separated instruction/data bus. The VGA Controller can display RCB data on a CRT or LCD monitor. The Debug Interface supports a debugging function for the Platform. The SRAM Interface supports 18-bit address bus and 32-bit data bus. The UART provides RS232 protocol, which supports serial communication function. The Platform is design and verified on a Xilinx VERTEX-4 XC4VLX80 FPGA board. Test code is generated by a cross compiler' and JTAG utility software and gdb are used to download the test code to the FPGA board through parallel cable. Finally, the Platform is implemented into a single ASIC chip using Chatered 0.18um process and it can operate at 100MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.4 s.316
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• pp.27-34
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• 2007

In this paper device driver for camera capture in hand held mobile system is implemented based on microsoft windows CE operating system. We also study the storage device driver based on the FAT fie system by using NAND flash memory as a storage device. We use the MBA2440 PDA board for implementing the hardware for image capture by using CMOS camera module producted by PixelPlus company. This camera module has VGA $640{\times}480$ pixel resolution. We also make application program which can be cooperated with the device driver for testing its performance, for example image capture speed and quality of captured image. We check that the application can be cooperated well not only with the device driver for camera capture but also with the device driver for FAT file system designed especially for the NAND flash memory.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.190-192
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• 2007

모바일 장치에서 사용하는 카메라 모듈을 가지고 MBA2440 보드에서 WINDOWS CE 운영체제의 디바이스 드라이버를 통하여 카메라 장치로부터 동영상 데이터를 얻어 화면에 표시하고, 여기서 획득된 화면정보를 Nand Flash 메모리에 저장하는 내용을 다룬다. 테스트에 사용된 카메라 모듈은 PIXELPLUS사의 모바일용 초소형 VGA급 30만 화소 카메라로 카메라모듈과 MBA2440보드 사이에 하드웨어적인 부분이 정상 작동하는지 확인을 위하여 펌웨어 상에서 카메라의 동영상 화면을 캡쳐하는 프로그램을 만들고, 이를 FAT File System을 이용하여 Nand Flash에 Image 파일 형태로 저장할 수 있도록 한다.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.4
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• pp.263-269
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• 2010

This paper describes real-time detection and tracking of moving objects for unmanned visual surveillance. Using images obtained from the fixed camera it detects moving objects within the image and tracks them with displaying rectangle boxes enclosing the objects. Tracking method is implemented on an embedded system which consists of TI DSK645.5 kit and the FPGA board connected on the DSP kit. The DSP kit processes image processing algorithms for detection and tracking of moving objects. The FPGA board designed for image acquisition and display reads the image line-by-line and sends the image data to DSP processor, and also sends the processed data to VGA monitor by DMA data transfer. Experimental results show that the tracking of moving objects is working satisfactorily. The tracking speed is 30 frames/sec with 320x240 image resolution.

• Spatial Information Research
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• v.2 no.2
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• pp.107-116
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• 1994

Choropleth map is a type of thematic maps in which areal units are shaded with a color or pattern that symbolizes some characteristic of the mapped unit. CMS was first developed to produce choropleth maps on ordinary microcomputer environments in 1988. Since then there have been significant technological developments and enhancements in user environments, which have affected the field of choropleth mapping systems posi¬tively. A new version of CMS was developed in accordance with these changes. CMS II requires an IBM PC, or compatible, with the minimum 640KB memory and VGA graphic board. It supports HP laser jet printers to output a high resolution map. The program can use Hangul letters for main menu, map title, and legend. And dBase file format (DEW) was implemented to exchange attribute files effectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.503-506
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• 2015

In accordance with IoT(Internet of Things) commercialization, the need to design SoC-based hardware platform with wireless communication is increasing. This paper therefor proposes an SoC platform architecture with Smart Frame System inter-communicating between devices. Wireless communication functions and high-performance real-time image processing hardware structure was applied to existing digital photo frame. We developed a smart phone application to control the smart frame through Bluetooth communication. The SoC platform hardware consists of CIS controller, Memory controller, ISP(Image Signal Processing) module for image scaling, Bluetooth Interface for inter-communicating between devices, VGA/TFT-LCD controller for displaying video. The Smart Frame System to support the IoT services was implemented and verified using HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA. The operating frequency is 54MHz.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.5
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• pp.151-161
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• 2009

Audio Video Standard (AVS) is the audio and video compression standard that was developed for domestic video applications in China. AVS employs low complexity tools to minimize degradation of RD performance of the state-the-art video codec, H.264/AVC. The AVS video codec consists of $8{\times}8$ block prediction and the same size transform to improve compression efficiency for VGA and higher resolution sequences. Currently, the AVS has been adopted more and more for IPTV services and mobile applications in China. So, many consumer electronics companies and multimedia-related laboratories have been developing applications and chips for the AVS. In this paper, we implemented the AVS video decoder and optimize it on TI's Davinci EVM DSP board. For improving the decoding speed and clocks, we removed unnecessary memory operations and we also used high-speed VLD algorithm, linear assembly, intrinsic functions and so forth. Test results show that decoding speed of the optimized decoder is $5{\sim}7$ times faster than that of the reference software (RM 5.2J).