• Title/Summary/Keyword: VCSEL

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Optimum Implant Depth and Its Determination in Implanted Vertical Cavity Surface Emitting Lasers (임플랜트된 표면 방출형 레이저에서 최적 임플랜트 깊이와 최적 깊이 판정 방법)

  • 안세환;김상배
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.8
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    • pp.45-50
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    • 2004
  • The characteristics and reliability of implanted VCSELs are greatly influenced by the thickness of the semi-insulating layer made by ion implantation for the current confinement. We propose a simple and purely electrical method of estimating the optimum implant depth, and find that the implant front should be located 2-DBR periods above the 1 - λ cavity in order to obtain simultaneously the low threshold current and high reliability.

Tailoring the Static Characteristics of Implanted VCSELs with the Implant and Metal Aperture Radii (임플랜트 및 금속전극 반경에 따른 임플랜트 VCSEL 정특성의 변화)

  • Kim, Tae-Yong;Kim, Sang-Bae;Park, Bun-Jae;Son, Jeong-Hwan
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.7
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    • pp.37-41
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    • 2004
  • We have formulated an empirical analytic model for the static characteristics of implanted vertical-cavity surface-emitting lasers (VCSELs). Specifically, we have derived analytic formulas for the threshold current, slope efficiency, dynamic resistance, and the output power and forward voltage at the operation current of 12 ㎃ in terms of the implant and metal-aperture radii by fitting the measured results. The radii of the metal aperture and implant mask of the 850 nm VCSELs range from 4 to 12.5 ${\mu}{\textrm}{m}$ and 7 to 17.5 ${\mu}{\textrm}{m}$ respectively. The model shows the way of tailoring the VCSEL characteristics by changing the mask dimensions only.

Optimum thickness of GaAs top layer in AlGaAs-based 850 nm VCSELs for 56 Gb/s PAM-4 applications

  • Yu, Shin-Wook;Kim, Sang-Bae
    • ETRI Journal
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    • v.43 no.5
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    • pp.923-931
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    • 2021
  • We studied the influence of GaAs top-layer thickness on the small-signal modulation response and 56 Gb/s four-level pulse-amplitude modulation eye quality of 850 nm vertical-cavity surface-emitting lasers (VCSELs). We considered the proportionality of the gain-saturation coefficient to the photon lifetime. The simulation results that employed the transfer-matrix method and laser rate equations led to the conclusion that the proportionality should be considered for proper explanation of the experimental results. From the obtained optical eyes, we could determine an optimum thickness of the GaAs top layer that rendered the best eye quality of VCSEL. We also compared two results: one result with a fixed gain-saturation coefficient and the other that considered the proportionality. The former result with the constant gain-saturation coefficient demonstrated a better eye quality and a wider optimum range of the GaAs top-layer thickness because the resultant higher damping reduced the relaxation oscillation.

Relationship between Transverse-Mode Behavior and Dynamic Characteristics in Multi-Mode VCSELs (다중모드 VCSEL의 모드 특성과 동특성 사이의 관계)

  • Kim Bong-Seok;Kim Sang-Bae
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.12
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    • pp.19-26
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    • 2005
  • We have studied the relationship between static mode behavior and dynamic characteristics of multiple transverse-mode VCSELs by measuring the modal L-I and I-V characteristics. Dependence of the resonance frequencies of RIN (relative intensity noise) spectra on the injection current can be understood by modal L-I characteristics and mode-coupling effects. Each transverse mode behaves as an independent diode laser with the different threshold current in large active-area VCSELs, and the multiple-step turn-on is observed when step-current input is applied. This multiple-step turn-on is a result of different turn-on delay times of the transverse modes. Since the multiple-step turn-on increases the rise-time significantly, the wide active-area VCSELs are not suitable for high-speed optical transmitters unless the input current is adjusted for single transverse-mode operation.

Implementation of 10 Gb/s 4-Channel VCSELs Driver Chip for Output Stabilization Based on Time Division Sensing Method (시분할 센싱 기법 기반의 출력 안정화를 위한 10 Gb/s 4채널 VCSELs 드라이버의 구현)

  • Yang, Choong-reol;Lee, Kang-yoon;Lee, Sang-soo;Jung, Whan-seok
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.40 no.7
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    • pp.1347-1353
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    • 2015
  • We implemented a 10 Gb/s 4-channel vertical cavity surface emission lasers (VCSEL) driver array in a $0.13{\mu}m$ CMOS process technology. To enhance high current resolution, power dissipation, and chip space area, digital APC/AMC with time division sensing technology is primarily adopted. The measured -3 dB frequency bandwidth is 9.2 GHz; the small signal gain is 10.5 dB; the current resolution is 0.01 mA/step, suitable for the wavelength operation up to 10 Gb/s over a wide temperature range. The proposed APC and AMC demonstrate 5 to 20 mA of bias current control and 5 to 20 mA of modulation current control. The whole chip consumes 371 mW of low power under the maximum modulation and bias currents. The active chip size is $3.71{\times}1.3mm^2$.

A 4-Channel Multi-Rate VCSEL Driver with Automatic Power, Magnitude Calibration using High-Speed Time-Interleaved Flash-SAR ADC in 0.13 ㎛ CMOS

  • Cho, Sunghun;Lee, DongSoo;Lee, Juri;Park, Hyung-Gu;Pu, YoungGun;Yoo, Sang-Sun;Hwang, Keum Cheol;Yang, Youngoo;Park, Cheon-Seok;Lee, Kang-Yoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.3
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    • pp.274-286
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    • 2016
  • This paper presents a 4-channel multi-rate vertical-cavity surface-emitting laser (VCSEL) driver. In order to keep the output power constant with respect to the process, voltage, temperature (PVT) variations, this research proposes automatic power and magnitude. For the fast settling time, the high-speed 10-bit time-interleaved Flash-successive approximation analog to digital converter (Flash-SAR ADC) is proposed and shared for automatic power and magnitude calibration to reduce the die area and power consumption. This chip is fabricated using $0.13-{\mu}m$ CMOS technology and the die area is $4.2mm^2$. The power consumption is 117.84 mW per channel from a 3.3 V supply voltage at 10 Gbps. The measured resolution of bias /modulation current for APC/AMC is 0.015 mA.