• Title/Summary/Keyword: Ultra-thinned Wafer

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Effect of Si Wafer Ultra-thinning on the Silicon Surface for 3D Integration (삼차원 집적화를 위한 초박막 실리콘 웨이퍼 연삭 공정이 웨이퍼 표면에 미치는 영향)

  • Choi, Mi-Kyeung;Kim, Eun-Kyung
    • Journal of the Microelectronics and Packaging Society
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    • v.15 no.2
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    • pp.63-67
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    • 2008
  • 3D integration technology has been a major focus of the next generation of IC industries. In this study Si wafer ultra-thinning has been investigated especially for the effect of ultra-thinning on the silicon surface. Wafers were grinded down to $30{\mu}m\;or\;50{\mu}m$ thickness and then grinded only samples were compared with surface treated samples in terms of surface roughness, surface damages, and hardness. Dry polishing or wet etching treatment has been applied as a surface treatment. Surface treated samples definitely showed much less surface damages and better roughness. However, ultra-thinned Si samples have the almost same hardness as a bulk Si wafer.

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Reduction of surface roughness during high speed thinning of silicon wafer

  • Heo, W.;Ahn, J.H.;Lee, N.E.
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.02a
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    • pp.392-392
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    • 2010
  • In this study, high-speed chemical dry thinning process of Si wafer and evolution of surface roughness were investigated. Direct injection of NO gas into the reactor during the supply of F radicals from $NF_3$ remote plasmas was very effective in increasing the Si thinning rate due to the NO-induced enhancement of surface reaction but thinned Si surface became roughened significantly. Addition of Ar gas, together with NO gas, decreased root mean square (RMS) surface roughness of thinned Si wafer significantly. The process regime for the thinning rate enhancement with reduced surface roughness was extended at higher Ar gas flow rate. Si wafer thinning rate as high as $22.8\;{\mu}m/min$ and root-mean-squared (RMS) surface roughness as small as 0.75 nm could be obtained. It is expected that high-speed chemical dry thinning process has possibility of application to ultra-thin Si wafer thinning with no mechanical damage.

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Ultra-Thinned Si Wafer Processing for Wafer Level 3D Packaging (웨이퍼 레벨 3D 패키징을 위한 초박막 Si 웨이퍼 공정기술)

  • Choi, Mi-Kyeung;Kim, Eun-Kyung
    • Journal of Welding and Joining
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    • v.26 no.1
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    • pp.12-16
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    • 2008
  • 본 보고에서는 3D 패키징에서 중요한 공정의 하나인 초박막 Si 웨이퍼 Thinning 공정에 대해 간략히 소개하였고, 표면처리에 대해 살펴보았다. 기계적, 특히 전기적 Damage를 줄이기 위한 최적화된 Thinning 공정과 신뢰성 분석 및 평가, 그리고 초박막 웨이퍼 핸들링 방법 등이 시스템적으로 개발되는 것이 중요하다. 칩 소형화 추세와 더불어 3D 패키징 기술이 중요시되는 산업 요구에 맞추어 향후 웨이퍼 Thinning 기술을 포함한 3D 기술의 핵심 공정기술들은 그 중요성이 증대할 것이고, 이에 대한 활발한 연구가 진행되리라 기대한다.