• New & Renewable Energy
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• v.20 no.1
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• pp.116-125
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• 2024

Ultra-low-head is an unexplored classification among the sites in which hydroelectric power can be produced. This is typically owing to the low power output and the economic value of the turbines available in this segment. A turbine capable of operating in an ultra-low-head condition without the need of a dam to produce electricity is developed in this study. A gate structure installed at a shallow water channel acting as a weir generates artificial head for the turbine mounted on the gate to produce power. The turbine and generator are designed to be compact and submersible for an efficient and silent operation. The gate angle is adjustable to operate the turbine at varying flow rates. The turbine is designed and tested using computational fluid dynamics tools prior to manufacturing and experimental studies. A parametric study of the runner blade parameters is conducted to obtain the most efficient blade design with minimal hydraulic losses. These parameters include the runner stagger and runner leading edge flow angles. The selected runner design showed improved hydraulic characteristics of the turbine to operate in an ultra-low-head site with minimal losses.

• Journal of Internet of Things and Convergence
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• v.6 no.2
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• pp.11-18
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• 2020

Since the end devices of the Internet of Things (IoT) are battery operated products, careful consideration for ultra-low power (ULP) is required. The Micro Controller Unit (MCU) industry has developed very effective functions to save energy, but developers have difficulty in selecting the MCU because various operating modes are applied to reduce energy consumption by manufacturers. Therefore, this paper introduces ULPMark benchmark, a standardized benchmark method that can compare MCUs of various vendors and feature sets, and provides hardware functions for ultra-low-power operation of the two platforms that received the high evaluation scores from ULPMark. In addition, we investigated and analyzed how developers can utilize the functions for ultra low power consumption through driver APIs and detailed register control.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.159-165
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• 2016

Recently, active efforts are being made for future Si CMOS technology by various researches on emerging devices and materials. Capability of low power consumption becomes increasingly important criterion for advanced logic devices in extending the Si CMOS. In this work, a junctionless field-effect transistor (JLFET) with ultra-thin poly-Si (UTP) channel is designed aiming the sub-10-nm technology for low-power (LP) applications. A comparative study by device simulations has been performed for the devices with crystalline and polycrystalline Si channels, respectively, in order to demonstrate that the difference in their performances becomes smaller and eventually disappears as the 10-nm regime is reached. The UTP JLFET would be one of the strongest candidates for advanced logic technology, with various virtues of high-speed operation, low power consumption, and low-thermal-budget process integration.

• ETRI Journal
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• v.31 no.2
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• pp.243-245
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• 2009

A novel ultra-low-power readout circuit for a pH-sensitive ion-sensitive field-effect transistor (ISFET) is proposed. It uses an ISFET/reference FET (REFET) differential pair operating in weak-inversion and a simple current-mode metal-oxide semiconductor FET (MOSFET) translinear circuit. Simulation results verify that the circuit operates with excellent common-mode rejection ability and good linearity for a single pH range from 4 to 10, while only 4 nA is drawn from a single 1 V supply voltage.

• Transactions on Semiconductor Engineering
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• v.2 no.1
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• pp.9-16
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• 2024

This paper discusses the design of bio-implanted ultra-low-power MICS RF transceivers for wireless sensor networks. The 400 MHz MICS standard was considered for the implementation of the WBAN wireless sensor system, indirectly minimizing radio propagation losses in the human body and the inference with surrounding networks. This paper includes link budget, various transmission and reception architectures for a system design and ultra-low power transceiver circuit techniques for the implementation of RF transceivers that meet MICS standards.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.625-626
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• 2006

An Ultra low power super-regenerative oscillator was implemented with on-chip inductor and quench signal generator. The super-regenerative oscillator detects the signal level as low as -70dBm while consuming only 0.48mA at 1.5V supply voltage. These results indicate that the super-regenerative oscillator can be outstanding candidate the simple, ultra low power receiver design.

• Progress in Superconductivity and Cryogenics
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• v.8 no.1
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• pp.26-28
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• 2006

The development technique of digital logic using CMOS device is close reached several limitations These make technical needs that are ultra high speed superconductive systems based on CMOS silicon digital computing technique. Comparing digital logic based on silicon CMOS, the computing technique based on ultra high speed superconductive systems has many advantages which are ultra low power consumption, ultra high operation speed. etc. It is estimated that features like these increasingly improve the possibility of ultra low power and ultra superconductive systems. In this paper digital logics of current CMOS technique and RSFQ superconductive technique are compared with and analyzed.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.3
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• pp.199-204
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• 2021

Ultra-compact electric vehicles have narrow space for power conversion devices. This work presents schemes to achieve the high-power density of a low-voltage DC-DC converter (LDC): simplifying a converter structure by using sync-buck topology, applying a planar inductor using PCB winding, and applying a plate-type heat sink. The heat sink is placed between two PCBs, which increases the contact surface between the PCB and the heat-dissipating device. It enables the miniaturization of the converter to improve the conditions of heat radiation. The validity of the proposed scheme is verified through the experiment using a 500 W(12 V, 41.67 A) prototype with an input voltage range from 58 V to 84 V.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.210-216
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• 2004

In this paper, we propose a noncoherent On-Off Keying (OOK) Ultra Wide Band (UWB) system based on power detection with noise power calibration for low power applications. The proposed UWB system achieves good bit error rate performance which is favorably comparable to that of the system using the ideal adaptive threshold, while maintaining simple receiver structure, In addition, low power Analog Front-End (AFE) blocks for the proposed noncoherent UWB transceiver are proposed and verified using CMOS technology. Simulation results on the pulse generator, delay time generator and 1-bit Analog-to-Digital (AID) converter show feasibility of the proposed UWB AFE system.

• Electronics and Telecommunications Trends
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• v.33 no.6
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• pp.24-33
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• 2018

In the age of IoT, in which everything is connected to a network, there have been increases in the amount of data traffic, latency, and the risk of personal privacy breaches that conventional cloud computing technology cannot cope with. The idea of edge computing has emerged as a solution to these issues, and furthermore, the concept of ultra-low power edge intelligent semiconductors in which the IoT device itself performs intelligent decisions and processes data has been established. The key elements of this function are an intelligent semiconductor based on artificial intelligence, connectivity for the efficient connection of neurons and synapses, and a large-scale spiking neural network simulation framework for the performance prediction of a neural network. This paper covers the current trends in ultra-low power edge intelligent semiconductors including issues regarding their technology and application.