• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.391-394
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• 2004

In this study, highly thermal stable Ni Germanosilicide has been utilized using NiPt alloy and novel NiPt/Co/TiN tri-layer. And, the Ni Germanosilicide Properties were characterized according to different Ge ratio (x) in $Si_{l-x}Ge_x$ for the next generation CMOS application. The sheet resistance of Ni Germanosilicide utilizing pure-Ni increased dramatically after the post-silicidation annealing at $600^{\circ}C$ for 30 min. Moreover, more degradation was found as the Ge fraction increases. However, using the proposed NiPt/Co/TiN tri-layer, low temperature silicidation and wide range of RTP process window were achieved as well as the improvement of the thermal stability according to different Ge fractions by the subsequent Co and TiN capping layer above NiPt on the $Si_{l-x}Ge_x$. Therefore, highly thermal immune Ni Germanosilicide up to $600^{\circ}C$ for 30 min is utilized using the NiPt/Co/TiN tri-layer promising for future SiGe based ULSI technology.

• 마이크로전자및패키징학회지
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• 제11권3호
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• pp.9-15
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• 2004

PMSSQ (Poly Methyl Silsesquioxane)-based matrix에 BTMSE (Bis Tri Methoxy Silyl Ethane) 를 첨가한 low-k물질의 전기적 특성을 조사하였다. 우리는 절연체로 copolymer를 사용하여 금속-절연체 -실리콘 구조를 만들고 BTS 실험을 통하여 누설 전류와 파괴 시간을 측정하였다. 코 폴리머의 기공이 $30\%$ 이상이 되었을 때, 파괴 시간이 급속하게 감소되어 진다. 온도에 관하여 파괴 시간으로부터 코 폴리머를 통한 구리 확산의 활성화 에너지는 1.51eV가 측정되었다.

• 마이크로전자및패키징학회지
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• 제11권3호
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• pp.91-97
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• 2004

PZT 박막을 rf-마그네트론 스퍼터링으로 $Pt/Ti/SiO_2/Si$ 기판 위에 형성시켰다. $5\%$ 과잉 PbO 를 포함한 bulk PZT 타겟을 사용하였다. 상온에서 PZT 박막을 얇게 입힌 후 나머지 두께를 $650^{\circ}C$에서 in-situ 방법으로 형성시켰다. 강유전 특성을 갖는 PZT 상은 $650^{\circ}C$에서 형성되었다. 2단계 스퍼터링에 의해 누설전류 특성을 크게 증진시킬 수 있었고, 적절한 두께의 상온층을 포함시킨 경우 $2{\times}10^{-7}A/cm^2$의 매우 작은 누설전류를 나타냈다. 누설전류 기구에 대한 조사 결과, 여러 조건에서 제조된 PZT 박막의 전기전도는 모두 bulk-limit 기구에 의한 것임을 알 수 있었다.

• Journal of Korean Vacuum Science & Technology
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• 제5권1호
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• pp.11-18
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• 2001

Dielectric passivation effects on the EM(electromigration) have been a great interest with recent ULSI and multilevel structure tends in thin film interconnections of a microelectronic device. SiO$_2$, PSG(phosphosilicate glass), and Si$_3$N$_4$ passivation materials effects on the EM resistance were investigated by utilizing widely used Al-1%Si thin film interconnections. A standard photolithography process was applied for the fabrication of 0.7㎛ thick 3㎛ wide, and 200㎛ ~1600㎛ long Al-1%Si EM test patterns. SiO$_2$, PSG, and Si$_3$N$_4$ dielectric passivation with the thickness of 300 nm were singly deposited onto the Al-1%Si thin film interconnections by using an APCVD(atmospheric pressure chemical vapor deposition) and a PECVD(plasma enhanced chemical vapor deposition) in order to investigate the passivation materials effects on the EM characteristics. EM tests were performed at the direct current densities of 3.2 $\times$ 10$\^$6/∼4.5 $\times$ 10$\^$6/ A/cm$^2$ and at the temperatures of 180 $\^{C}$, 210$\^{C}$, 240$\^{C}$, and 270$\^{C}$ for measuring the activation energies(Q) and for accelerated test conditions. Activation energies were calculated from the measured MTF(mean-time-to-failure) values. The calculated activation energies for the electromigration were 0.44 eV, 0.45 eV, and 0.50 eV, and 0.66 eV for the case of nonpassivated-, Si$_3$N$_4$passivated-, PSG passivated-, and SiO$_2$ passivated Al-1%Si thin film interconnections, respectively. Thus SiO$_2$ passivation showed the best characteristics on the EM resistance followed by the order of PSG, Si$_3$N$_4$ and nonpassivation. It is believed that the passivation sequences as well as the passivation materials also influence on the EM characteristics in multilevel passivation structures.

• 대한전기학회논문지:시스템및제어부문D
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• 제49권6호
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• pp.322-329
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• 2000

BIST(Built-in Self Test) has been considered as the most promising DFT(design-for-test) scheme for the present and future test strategy. The most serious problem in applying BIST(Built-in Self Test) into a large circuit is the excessive increase in test time. This paper is focused on this problem. We proposed a new BIST construction scheme which uses a parallel divide-and-conquer method. The circuit division is performed with respect to some internal nodes called test points. The test points are selected by considering the nodal connectivity of the circuit rather than the testability of each node. The test patterns are generated by only one linear feedback shift register(LFSR) and they are shared by all the divided circuits. Thus, the test for each divided circuit is performed in parallel. Test responses are collected from the test point as well as the primary outputs. Even though the divide-and-conquer scheme is used and test patterns are generated in one LFSR, the proposed scheme does not lose its pseudo-exhaustive property. We proposed a selection procedure to find the test points and it was implemented with C/C++ language. Several example circuits were applied to this procedure and the results showed that test time was reduced upto 1/2151 but the increase in the hardware overhead or the delay increase was not much high. Because the proposed scheme showed a tendency that the increasing rates in hardware overhead and delay overhead were less than that in test time reduction as the size of circuit increases, it is expected to be used efficiently for large circuits as VLSI and ULSI.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 춘계학술발표대회
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• pp.41.2-41.2
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• 2011

Recently, scaling down of ULSI (Ultra Large Scale Integration) circuit of CMOS (Complementary Metal Oxide Semiconductor) based electronic devices become much faster speed and smaller size than ever before. However, very narrow interconnect line width causes some drawbacks. For example, deposition of conformal and thin barrier is not easy moreover metallization process needs deposition of diffusion barrier and glue layer. Therefore, there is not enough space for copper filling process. In order to overcome these negative effects, simple process of copper metallization is required. In this research, Cu-V thin alloy film was formed by using RF magnetron sputter deposition system. Cu-V alloy film was deposited on the plane $SiO_2$/Si bi-layer substrate with smooth and uniform surface. Cu-V film thickness was about 50 nm. Cu-V layer was deposited at RT, 100, 150, 200, and $250^{\circ}C$. XRD, AFM, Hall measurement system, and XPS were used to analyze Cu-V thin film. For the barrier formation, Cu-V film was annealed at 200, 300, 400, 500, and $600^{\circ}C$ (1 hour). As a result, V-based thin interlayer between Cu-V film and $SiO_2$ dielectric layer was formed by itself with annealing. Thin interlayer was confirmed by TEM (Transmission Electron Microscope) analysis. Barrier thermal stability was tested with I-V (for measuring leakage current) and XRD analysis after 300, 400, 500, 600, and $700^{\circ}C$ (12 hour) annealing. With this research, over $500^{\circ}C$ annealed barrier has large leakage current. However V-based diffusion barrier annealed at $400^{\circ}C$ has good thermal stability. Thus, thermal stability of vanadium-based thin interlayer as diffusion barrier is good for copper interconnection.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1993년도 춘계학술대회 논문집
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• pp.39-43
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• 1993

Electricial characteristics of gate dielectrics prepared by reoxidation of thermal $SiO_2$ in nitrous oxide gas have been investigated. 10 and 19nm-thick oxides were reoxidized at temperatures of $900-1000^{\circ}C$ for 10-60 min in $N_2O$ ambient. As reoxidation proceeds, it is shown that nitrogen concentration at $Si/SiO_2$ interface increases gradually through the AES analysis. Nitrogen pile-up at $Si/SiO_2$ interface acts as a oxidant diffusion barrier that reduces the oxidation rate significantly. And it not only strengthen oxynitride structure at the interface but improve the gate dielectric qualities. Reliabilities of oxynitride films are conformed by the breakdown distributions and constant current stress technique. Therefore, the oxynitride films made by this process show a good promise for future ULSI applications.

• 대한전자공학회논문지SD
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• 제39권5호
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• pp.1-7
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• 2002

Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.

• 마이크로전자및패키징학회지
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• 제10권3호
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• pp.89-98
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• 2003

반도체 소자의 배선용 재료로서 사용가능한 합금원소 Mg를 첨가한 Cu(Mg) 박막의 기계 및 전기적 특성 변화를 조사하였다. Cu(2.7at.%Mg) 박막은 열처리를 할 경우 Cu 박막에 비하여 표면거칠기는 약 1/10 정도로 줄고 $SiO_2$와의 접착력도 2배 이상 향상된 결과를 나타내었다. 또한 $300^{\circ}C$이상의 온도에서 10분 이상 열처리를 할 경우 급격한 저항감소를 보여주었는데 이는 Mg 원소의 확산으로 인해 표면 및 계면에서 Mg 산화물이 형성되고 내부에는 순수 Cu와 같이 되었기 때문이다. 경도 및 열응력에 대한 저항력도 Cu박막에 비해 우수한 것으로 나타났으며 열응력으로 인해 Cu 박막에 나타나던 표면 void가 Cu(Mg) 박막에서는 전혀 관찰되지 않았다. EM Test 결과 lifetime은 2.5MA/$cm^2$, $297^[\circ}C$에서 순수 Cu 라인보다 5배 이상 길고 BTS Test 결과 Capacitance-Voltage 그래프의 플랫 밴드 전압(V$_{F}$ )의 shift현상이 Cu에서는 나타났지만 Cu(Mg) 박막에서는 발생하지 않는 우수한 신뢰성을 보여주었다. 누설전류 측정을 통한 $SiO_2$의 파괴시간은 Cu에 비하여 약 3배 이상 길어 합금원소에 의한 확산방지 효과가 있음을 확인하였다.

• Tribology and Lubricants
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• 제31권3호
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• pp.79-85
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• 2015

RC delay is a critical issue for achieving high performance of ULSI devices. In order to minimize the RC delay time, we uses the CMP process to introduce high-conductivity Cu and low-k materials on the damascene. The low-k materials are generally soft and fragile, resulting in structure collapse during the conventional high-pressure CMP process. One troubleshooting method is electrochemical mechanical polishing (ECMP) which has the advantages of high removal rate, and low polishing pressure, resulting in a well-polished surface because of high removal rate, low polishing pressure, and well-polished surface, due to the electrochemical acceleration of the copper dissolution. This study analyzes an electrochemical state (active, passive, transpassive state) on a potentiodynamic curve using a three-electrode cell consisting of a working electrode (WE), counter electrode (CE), and reference electrode (RE) in a potentiostat to verify an electrochemical removal mechanism. This study also tries to find optimum conditions for ECMP through experimentation. Furthermore, during the low-pressure ECMP process, we investigate the effect of current density on surface roughness and removal rate through anodic oxidation, dissolution, and reaction with a chelating agent. In addition, according to the Faraday’s law, as the current density increases, the amount of oxidized and dissolved copper increases. Finally, we confirm that the surface roughness improves with polishing time, and the current decreases in this process.