• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.391-394
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• 2004

In this study, highly thermal stable Ni Germanosilicide has been utilized using NiPt alloy and novel NiPt/Co/TiN tri-layer. And, the Ni Germanosilicide Properties were characterized according to different Ge ratio (x) in $Si_{l-x}Ge_x$ for the next generation CMOS application. The sheet resistance of Ni Germanosilicide utilizing pure-Ni increased dramatically after the post-silicidation annealing at $600^{\circ}C$ for 30 min. Moreover, more degradation was found as the Ge fraction increases. However, using the proposed NiPt/Co/TiN tri-layer, low temperature silicidation and wide range of RTP process window were achieved as well as the improvement of the thermal stability according to different Ge fractions by the subsequent Co and TiN capping layer above NiPt on the $Si_{l-x}Ge_x$. Therefore, highly thermal immune Ni Germanosilicide up to $600^{\circ}C$ for 30 min is utilized using the NiPt/Co/TiN tri-layer promising for future SiGe based ULSI technology.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.3 s.32
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• pp.9-15
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• 2004

We investigated the electrical properties of copolymer low-k materials that are compromised of the PMSSQ(Poly Methyl Silsesquioxane)-based matrix with the BTMSE (Bis Tri Methoxy Silyl Ethane) additives. We manufactured MIS-type test samples using the copolymer as the insulator and measured their leakage current and failure time by means of the BTS (bias-temperature-stress) test. The failure time was observed to decrease drastically when the porosity of the copolymer was increased over $30\%$. From the measurement of failure time with respect to temperature. the activation energy of Cu drift through the copolymer was calculated to be 1.51 eV.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.3 s.32
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• pp.91-97
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• 2004

PBT thin films were formed by rf-magnetron sputtering on $Pt/Ti/SiO_2/Si$ substrate. Bulk-PZT target containing $5\%$-excess PbO was used. After PZT thin films had been deposited at room temperature, remaining portion of the thin film was formed by in-situ process. The ferroelectric perovskite phase was formed at $650^{\circ}C$. The leakage current property was improved dramatically by 2-step sputtering, and in the sample containing optimum thickness of room temp.-layer very low leakage current of $2{\times}10^{-7}A/cm^2$ was shown. As a result of the investigation on the leakage current mechanism, the electrical conduction mechanism in all PZT thin films formed by several conditions was confirmed as bulk-limited mechanism.

• Journal of Korean Vacuum Science & Technology
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• v.5 no.1
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• pp.11-18
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• 2001

Dielectric passivation effects on the EM(electromigration) have been a great interest with recent ULSI and multilevel structure tends in thin film interconnections of a microelectronic device. SiO$_2$, PSG(phosphosilicate glass), and Si$_3$N$_4$ passivation materials effects on the EM resistance were investigated by utilizing widely used Al-1%Si thin film interconnections. A standard photolithography process was applied for the fabrication of 0.7㎛ thick 3㎛ wide, and 200㎛ ~1600㎛ long Al-1%Si EM test patterns. SiO$_2$, PSG, and Si$_3$N$_4$ dielectric passivation with the thickness of 300 nm were singly deposited onto the Al-1%Si thin film interconnections by using an APCVD(atmospheric pressure chemical vapor deposition) and a PECVD(plasma enhanced chemical vapor deposition) in order to investigate the passivation materials effects on the EM characteristics. EM tests were performed at the direct current densities of 3.2 $\times$ 10$\^$6/∼4.5 $\times$ 10$\^$6/ A/cm$^2$ and at the temperatures of 180 $\^{C}$, 210$\^{C}$, 240$\^{C}$, and 270$\^{C}$ for measuring the activation energies(Q) and for accelerated test conditions. Activation energies were calculated from the measured MTF(mean-time-to-failure) values. The calculated activation energies for the electromigration were 0.44 eV, 0.45 eV, and 0.50 eV, and 0.66 eV for the case of nonpassivated-, Si$_3$N$_4$passivated-, PSG passivated-, and SiO$_2$ passivated Al-1%Si thin film interconnections, respectively. Thus SiO$_2$ passivation showed the best characteristics on the EM resistance followed by the order of PSG, Si$_3$N$_4$ and nonpassivation. It is believed that the passivation sequences as well as the passivation materials also influence on the EM characteristics in multilevel passivation structures.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.6
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• pp.322-329
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• 2000

BIST(Built-in Self Test) has been considered as the most promising DFT(design-for-test) scheme for the present and future test strategy. The most serious problem in applying BIST(Built-in Self Test) into a large circuit is the excessive increase in test time. This paper is focused on this problem. We proposed a new BIST construction scheme which uses a parallel divide-and-conquer method. The circuit division is performed with respect to some internal nodes called test points. The test points are selected by considering the nodal connectivity of the circuit rather than the testability of each node. The test patterns are generated by only one linear feedback shift register(LFSR) and they are shared by all the divided circuits. Thus, the test for each divided circuit is performed in parallel. Test responses are collected from the test point as well as the primary outputs. Even though the divide-and-conquer scheme is used and test patterns are generated in one LFSR, the proposed scheme does not lose its pseudo-exhaustive property. We proposed a selection procedure to find the test points and it was implemented with C/C++ language. Several example circuits were applied to this procedure and the results showed that test time was reduced upto 1/2151 but the increase in the hardware overhead or the delay increase was not much high. Because the proposed scheme showed a tendency that the increasing rates in hardware overhead and delay overhead were less than that in test time reduction as the size of circuit increases, it is expected to be used efficiently for large circuits as VLSI and ULSI.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.41.2-41.2
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• 2011

Recently, scaling down of ULSI (Ultra Large Scale Integration) circuit of CMOS (Complementary Metal Oxide Semiconductor) based electronic devices become much faster speed and smaller size than ever before. However, very narrow interconnect line width causes some drawbacks. For example, deposition of conformal and thin barrier is not easy moreover metallization process needs deposition of diffusion barrier and glue layer. Therefore, there is not enough space for copper filling process. In order to overcome these negative effects, simple process of copper metallization is required. In this research, Cu-V thin alloy film was formed by using RF magnetron sputter deposition system. Cu-V alloy film was deposited on the plane $SiO_2$/Si bi-layer substrate with smooth and uniform surface. Cu-V film thickness was about 50 nm. Cu-V layer was deposited at RT, 100, 150, 200, and $250^{\circ}C$. XRD, AFM, Hall measurement system, and XPS were used to analyze Cu-V thin film. For the barrier formation, Cu-V film was annealed at 200, 300, 400, 500, and $600^{\circ}C$ (1 hour). As a result, V-based thin interlayer between Cu-V film and $SiO_2$ dielectric layer was formed by itself with annealing. Thin interlayer was confirmed by TEM (Transmission Electron Microscope) analysis. Barrier thermal stability was tested with I-V (for measuring leakage current) and XRD analysis after 300, 400, 500, 600, and $700^{\circ}C$ (12 hour) annealing. With this research, over $500^{\circ}C$ annealed barrier has large leakage current. However V-based diffusion barrier annealed at $400^{\circ}C$ has good thermal stability. Thus, thermal stability of vanadium-based thin interlayer as diffusion barrier is good for copper interconnection.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1993.05a
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• pp.39-43
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• 1993

Electricial characteristics of gate dielectrics prepared by reoxidation of thermal $SiO_2$ in nitrous oxide gas have been investigated. 10 and 19nm-thick oxides were reoxidized at temperatures of $900-1000^{\circ}C$ for 10-60 min in $N_2O$ ambient. As reoxidation proceeds, it is shown that nitrogen concentration at $Si/SiO_2$ interface increases gradually through the AES analysis. Nitrogen pile-up at $Si/SiO_2$ interface acts as a oxidant diffusion barrier that reduces the oxidation rate significantly. And it not only strengthen oxynitride structure at the interface but improve the gate dielectric qualities. Reliabilities of oxynitride films are conformed by the breakdown distributions and constant current stress technique. Therefore, the oxynitride films made by this process show a good promise for future ULSI applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.1-7
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• 2002

Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.3
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• pp.89-98
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• 2003

The electrical and mechanical properties of sputtered Cu(Mg) films are investigated for highly reliable interconnects. The roughness, adhesion, hardness and resistance to thermal stress of Cu(Mg) film annealed in vacuum at $400^{\circ}C$ for 30min were improved than those of pure Cu film. Moreover, the flat band voltage(V$_{F}$ ) shift in the Capacitance-Voltage(C-V) curve upon bias temperature stressing(BTS) was not observed and leakage currents of Cu(Mg) into $SiO_2$ were three times less than those of pure Cu. Because Mg was easy to react with oxide than Cu and Si after annealing, the Mg Oxide which formed at surface and interface served as a passivation layer as well.

• Tribology and Lubricants
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• v.31 no.3
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• pp.79-85
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• 2015

RC delay is a critical issue for achieving high performance of ULSI devices. In order to minimize the RC delay time, we uses the CMP process to introduce high-conductivity Cu and low-k materials on the damascene. The low-k materials are generally soft and fragile, resulting in structure collapse during the conventional high-pressure CMP process. One troubleshooting method is electrochemical mechanical polishing (ECMP) which has the advantages of high removal rate, and low polishing pressure, resulting in a well-polished surface because of high removal rate, low polishing pressure, and well-polished surface, due to the electrochemical acceleration of the copper dissolution. This study analyzes an electrochemical state (active, passive, transpassive state) on a potentiodynamic curve using a three-electrode cell consisting of a working electrode (WE), counter electrode (CE), and reference electrode (RE) in a potentiostat to verify an electrochemical removal mechanism. This study also tries to find optimum conditions for ECMP through experimentation. Furthermore, during the low-pressure ECMP process, we investigate the effect of current density on surface roughness and removal rate through anodic oxidation, dissolution, and reaction with a chelating agent. In addition, according to the Faraday’s law, as the current density increases, the amount of oxidized and dissolved copper increases. Finally, we confirm that the surface roughness improves with polishing time, and the current decreases in this process.