• Journal of the Korean institute of surface engineering
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• v.29 no.5
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• pp.570-576
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• 1996

Cu films for future ULSI metallization were prepared by partially ionized beam (PIB) deposition and characterized in terms of preferred orientation, grain size, roughness and resistivity. PIB-Cu films were prepared on Si (100) at pressure of $8 \times 10^{-7}$~$1 \times 10^{-6}$ Torr. Effects of acceleration voltage and ionization potential on the properties of PIB-Cu films have been investigated. As the acceleration voltage increased at constant ionization potential of 400 V, the degree of preferred orientation and surface smoothness of the Cu film increased. At the ionization potential of 450 V, the degree of preferred orientation at the acceleration voltage higher than 2 kV decreased and surface roughness increased with acceleration voltage. Grain size of Cu films increased to 1100 $\AA$ initially up to applied acceleration voltage of 1 kV, above which a little increase occurred with the acceleration voltage. There was no indication of impurities such as C, O in all sample. Resistivity of Cu film had the same trends as the surface roughness with acceleration voltage and ionization potential. The increase of electrical resistivity of PIB-Cu films was explained in terms of grain size and surface roughness

• Journal of the Korean institute of surface engineering
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• v.36 no.1
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• pp.74-78
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• 2003

The corrosion failure of electronic devices has been a major reliability concern lately. This failure is an ongoing concern because of miniaturization of integrated circuits (IC) and the increased use of polymers in electronic packaging. Recently, plasma-polymerized cyclohexane films were considered as a possible candidate for a interlayer dielectric for multilever metallization of ultra large scale integrated (ULSI) semiconductor devices. In this paper the protective ability of above films as a function of deposition temperature and RF power in an 3.5 wt.% NaCl solution were examined by polarization measurement. The film was characterized by FTIR spectroscopy and contact angle measurement. The protective efficiency of the film increased with increasing deposition temperature and RF power, which induced the higher degree of cross-linking and hydrophobicity of the films.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.41-44
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• 2003

As the device feature size is reduced to the deep sub-micron regime, the chemical mechanical polishing (CMP) technology is widely recognized as the most promising method to achieve the global planarization of the multilevel interconnection for ULSI applications. However, cost of ownership (COO) and cost of consumables (COC) were relatively increased because of expensive slurry. In this paper, the effects of different slurry composition on the oxide CMP characteristics were investigated to obtain the higher removal rate and lower non-uniformity. We prepared the various kinds of slurry. In order to save the costs of slurry, the original slurry was diluted by de-ionized water (DIW). And then, alunima abrasives were added in the diluted slurry in order to promote the mechanical force of diluted slurry.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.5
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• pp.358-364
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• 1998

Retrograde well is a new process for ULSI fabrication. High energy ion implantation has been used for retrograde well formation. In this paper the forming condition for retrograde well using high energy ion implantation is compared with that for conventional well. TW signals for retrograde p-,n-well($900^{\circ}C$),after annealing are similar trends to those of conventional ones($1150^{\circ}C$), however the signals for RTA have the highest value because of small thermal budget. Junction depths of retrograde well are varied from about 1.2 to $3.0\{mu}m$ as for conventional well. The peak concentrations of retrograde well, however, are about 10 times higher in values than those of conventional ones so that they can be used as any types of potential barriers or gettering sites. The critical dose for phosphorus implantation in our experiments is between $3\times10^{13} and 1\times10^{14}/cm^2$. Under the above critical dose, there are many secondary defects near projected range such as dislocation lines and dislocation loops.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.15-18
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• 2003

Ta-Ti metal alloy is proposed for alternate gate electrode of ULSI MOS device. Ta-Ti alloy was deposited directly on $SiO_2$ by a co-sputtering method and good interface property was obtained. The sputtering power of each metal target was 100W. Thermal and chemical stability of the electrode was studied by annealing at $500^{\circ}C$ and $600^{\circ}C$ in Ar ambient. X-ray diffraction was measured to study interface reaction and EDX(energy dispersive X-ray) measurement was performed to investigate composition of Ta and Ti element. Electrical properties were evaluated on MOS capacitor, which indicated that the work function of Ta-Ti metal alloy was ${\sim}4.1eV$ compatible with NMOS devices. The measured sheet resistance of alloy was lower than that of poly silicon.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.247-251
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• 2004

Chemical-Mechanical Polishing(CMP) especially is becoming one of the most important ULSI processes for the 0.25m generation and beyond. And there are many elements affecting CMP performance such as slurry, pad, process parameters and pad conditioning. Among these elements the CMP pad is considered one of the most important because of its change. But the surface of the pad has irregular pores, so there is non-uniformity of slurry flow and of contact area between wafer and the pad, and glazing occurs on the surface of the pad. So we make CMP pad with micro structure using micro molding method. This paper introduces the basic concept and fabrication technique of CMP pad with micro-structure and the characteristic of polishing. Experimental results demonstrate the removal rate, uniformity, and time vs. removal rate.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.571-572
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• 2006

Tungsten CMP needs interconnect of semiconductor device ULSI chip and metal plug formation, CMP technology is essential indispensable method for local planarization. This Slurry development also for tungsten CMP is important, slurry of metal wiring material that is used present is depending real condition abroad. It is target that this research makes slurry of efficiency that overmatch slurry that is such than existing because focus and use colloidal silica by abrasive particle to internal production technology development. Compared selectivity of slurry that is developed with competitor slurry using 8" tungsten wafer and 8" oxide wafer in this experiment. And removal rate measures about density change of $H_2O_2$ and Fe particle. Also, corrosion potential and current density measure about Fe ion and Fe particle. As a result, selectivity find 83:1, and expressed similar removal rate and corrosion potential and current density value comparing with competitor slurry.

• Journal of the Korean Vacuum Society
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• v.9 no.3
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• pp.267-272
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• 2000

Electroplating Cu was deposited on Si(100) wafer after seed Cu was deposited by sputtering first. TaN was deposited as a diffusion barrier before depositing the seed Cu. Electroplating Cu thin films show highly (111)-oriented microstructure for both before and after annealing at $450^{\circ}C$ for 30min and no copper silicide was detected in the same samples, which indicates that TaN barrier layer blocks well the Cu diffusion into silicon substrate. After annealing the electroplating Cu film up to $450^{\circ}C$, the Cu film became columnar from non-columnar, its grain size became larger about two times, and also defects density of stacking faults, twins and dislocations decreased greatly. Thus the heat treatment will improve significantly electromigration property caused by the grain boundary in the Cu thin films.

• Vacuum Magazine
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• v.3 no.3
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• pp.15-18
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• 2016

In future wearable electronic systems, 3-dimensional (3D) devices have attracted much attention due to their high density integration and low-power functionality. Among 3D devices, gate-all-around (GAA) nanowire transistor provides superior gate controllability, resulting in suppressing short channel effect and other drawbacks in 2D metal-oxide-semiconductor field-effect transistor (MOSFET). Silicon nanowires (SiNWs) are the most promising building block for GAA structure device due to their compatibility with the current Si-based ultra large scale integration (ULSI) technology. Moreover, the theoretical limit for subthreshold swing (SS) of MOSFET is 60 mV/dec at room temperature, which causes the increase in Ioff current. To overcome theoretical limit for the SS, it is crucial that research into new types of device concepts should be performed. In our present studies, we have experimentally demonstrated feedback FET (FBFET) and tunnel FET (TFET) with sub-60 mV/dec based on SiNWs. Also, we fabricated SiNW based complementary TFET (c-TFET) and SiNW complementary metal-oxide-semiconductor (CMOS) inverter. Our research demonstrates the promising potential of SiNW electronic devices for future wearable electronic systems.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.26-31
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• 2023

We investigated the impact of NF₃ / H₂O remote plasma dry cleaning conditions on the SiO₂ etching rate at different preparation states during the fabrication of ultra-large-scale integration (ULSI) devices. This included consideration of factors like Si crystal orientation prior to oxidation and three-dimensional structures. The dry cleaning process were carried out varying the parameters of pressure, NF₃ flow rate, and H₂O flow rate. We found that the pressure had an effective role in controlling anisotropic etching when a thin SiO₂ layer was situated between Si₃N₄ and Si layers in a multilayer trench structure. Based on these observations, we would like to provide further guidelines for implementing the dry cleaning process in the fabrication of semiconductor devices having 3D structures.