• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2002.11a
• /
• pp.7-12
• /
• 2002

반도체 공정에서 구리(Cu) 배선의 미세구조와 신뢰성에 대해 연구하였는데, 특히 CVD Cu와 전기도금 Cu를 사용하여 신뢰성에 대한 texture와 결정 구조의 영향을 연구하였다 CVD Cu의 경우 여러 가지 시드층(seed layer)을 사용함으로서, 결정입자의 크기는 비슷하지만 texture가 전혀 다른 Cu 박막을 얻을 수 있었는데, 신뢰성 검사결과 (111) texture를 가진 Cu 배선의 수명이 (200) texture를 가진 Cu 배선의 수명보다 약 4배 가량 길게 나왔다. 전기도금 Cu 박막의 경우 항상 (111) texture를 갖고 있었으며 결정립의 크기도 CVD Cu의 것보다 더 컸다. Damascene 공법으로 회로 형성한 Cu 배선의 경우에도 전기도금 Cu의 결정립 크기가 CVD Cu의 것보다 더 크게 나타났으며, 신뢰성 검사결과 배선의 수명도 더 길게 나타났는데 그 차이는 0.4 $\mu\textrm{m}$ 이하의 미세선폭 영역에서 더욱 현저했다. 따라서 전기도금 Cu가 CVD Cu보다 신뢰성 측면에서 더 우수한 것으로 판명되었다.

• Journal of Korean Vacuum Science & Technology
• /
• v.7 no.2
• /
• pp.39-44
• /
• 2003

Recent ULSI and multilevel structure trends in microelectronic devices minimize the line width down to a quarter micron and below, which results in the high current densities in thin film interconnections. Under high current densities, an EM(electromigration) induced failure becomes one of the critical problems in a microelectronic device. This study is to improve thin film interconnection materials by investigating the EM characteristics in PSG(phosphosilicate glass)/SiO$_2$ passivated Al-l%Si thin film interconnections. Straight line patterns, wide and narrow link type patterns, and meander type patterns, etc. were fabricated by a standard photholithography process. The main results are as follows. The current crowding effects result in the decrease of the lifetime in thin film interconnections. The electric field effects accelerate the decrease of lifetime in the double-layered thin film interconnections. The lifetime of interconnections also depends upon the current conditions of P.D.C.(pulsed direct current) frequencies applied at the same duty factor.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.15 no.1
• /
• pp.1-6
• /
• 2002

The hot carried degradation in a metal oxide semiconductor device has been one of the most serious concerns for MOS-ULSI. In this paper, three types of LDD(lightly doped drain) structure for suppression of hot carried degradation, such as decreasing of performance due to spacer-induced degradation and increase of series resistance will be investigated. in this study, LDD-nMOSFETs used had three different drain structure, (1) conventional surface type LDD(SL), (2) Buried type LDD(BL), (3) Surface implantation type LDD(SI). As experimental results, the surface implantation the LDD structure showed that improved hot carrier lifetime to comparison with conventional surface and buried type LDD structures.

• Transactions on Electrical and Electronic Materials
• /
• v.4 no.6
• /
• pp.32-37
• /
• 2003

In this paper, the trap characteristics of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 113.4nm and 814nm, which have the gate area 10$\^$-3/ $\textrm{cm}^2$. The stress induced leakage currents will affect data retention, and the stress current and transient current is used to estimate to fundamental limitations on oxide thicknesses.

• Journal of electromagnetic engineering and science
• /
• v.4 no.2
• /
• pp.56-62
• /
• 2004

We present a multi-Gbit/s digital I/O interface based on RF-modulation and capacitive-coupling over an impedance matched transmission line. The RF-interconnect(RFI) can greatly reduce the digital switching noise and eliminate the dc power dissipation over the channel. It also enables reduced signal amplitude(as low as 200 ㎷) with enhanced data rate and affordable circuit overhead. This paper addresses the system advantages and implementation issues of RFI. A prototype on-chip RFI transceiver is implemented in 0.18-${\mu}{\textrm}{m}$ CMOS. It demonstrates a maximum data rate of 2.2 Gbit/s via 10.5-㎓ RF-modulation. The RFI can be very instrumental for future high-speed inter- and intra-ULSI data links.

• Journal of the Korean Society of Safety
• /
• v.13 no.3
• /
• pp.67-73
• /
• 1998

The technology for neutralizing static electricity by soft X-ray radiation has been newly developed. This technology involves ionization of gas molecules in the vicinity of a charged substrate to generate ions and electrons to reduce electrostatic potential. The ULSI device substrate and liquid crystal display substrate tend to get charged instantly to a high potential level when they are handled in the manufacturing process. Soft X-ray radiation is adequate in air or $O_2$ gas at atmospheric pressure. This newly developed neutralization method is effective to be superior to the conventional technique, i.e., an ionizer by using corona discharge ,in every aspect. The new method features excellent neutralization capability and is able to completely reduce electrostatic potential to 0 V within a short time. Moreover, this is a very clean antistatic technology free from particle generation ,ozone generation, and electromagnetic noise, which are problems in using the corona discharge ionizer.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• v.9 no.2
• /
• pp.303-306
• /
• 2005

High aspect ration via-hole etching process has emerged as one of the most crucial means to increase component density for ULSI devices. Because of charge accumulation in via hole, this sophisticated and important process still hold several problems, such as etching stop, loading effects during fabrication of integrated circuits. Indeed, the concern actually depends on accumulated charge. For monitoring accumulated charge during plasma etching process, charge-up monitoring sensor was fabricated and tested under some plasma conditions. This paper presents a neural network-based technique for analyzing and modeling several electrical performance of plasma charge-up monitoring sensor.

• Proceedings of the KIEE Conference
• /
• 2006.07c
• /
• pp.1727-1728
• /
• 2006

Chemical mechanical polishing (CMP) technology has been widely used for global planarization of multi-level interconnection for ULSI applications. However, the cost of ownership and cost of consumables are relatively high because of expensive slurry. In this paper, we studied the mixed abrasive slurry(MAS). In order to save the costs of slurry, the original silica slurry was diluted by do-ionized water (DIW). And then, $ZrO_2$,$CeO_2$, and $MnO_2$ abrasives were added in the diluted slurry in order to promote the mechanical force of diluted slurry. We have also investigate the possibility of mixed abrasive slurry for the oxide CMP application.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.13 no.11
• /
• pp.901-907
• /
• 2000

As the minimum feature size for making ULSI approaches the wavelength of light source in optical lithography, the aerial image is so hardly distorted because of the optical proximity effect that the accurate mask image reconstruction on wafer surface is almost impossible. We applied the Optical Proximity Correction(OPC) on isolated patterns assuming Attenuated Phase Shift Mask(APSM) as well as binary mask, to correct the widening of isolated patterns. In this study, we found that applying OPC to APSM shows much better improvement not only in enhancing the resolution and fidelity of t도 images but also in enhancing the process margin than applying OPC to the binary mask. Also, we propose the OPC method of APSM for isolated patterns, the size of which is less than the wavelength of the ArF excimer laser. Finally, we predicted the resolution limit of optical lithography through the aerial image simulation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2007.11a
• /
• pp.159-159
• /
• 2007

In order to reduce a signal delay in ULSI, low resistive metal and intermetal dielectric material of low dielectric constant are required. Ordered mesoporous silica film is proper to intermetal dielectric due to its low dielectric constant and superior mechanical properties. In this study, ordered mesoporous silica films was synthesized using TEOS (tetraethoxysilane) / MTES (methyltriethoxysilane) mixed silica precursor and Brij-$76^{(R)}$ surfactant. These films had the porosity of 40% and dielectric constant of 2.5. To lower dielectric constant, the ordered mesoporous silica films were surface-modified by HMDS (hexamethyldisilazane) treatment. HMDS substituted -OH groups on the surface of silica wall for -Si$(CH_3)_3$ groups. After the HMDS treatment, ordered mesoporous silica films were calcined at various calcination temperatures. Through the investigation, it was concluded that the proper calcination temperature is necessary as aspects of structural, electrical, and mechanical properties.