• Journal of Power Electronics
• /
• v.19 no.6
• /
• pp.1527-1535
• /
• 2019

Because of the shortcomings of the PID controllers and traditional drive systems of permanent magnet synchronous motors (PMSMs), a PMSM passivity-based control (PBC) drive system based on a quasi-Z source matrix converter (QZMC) is proposed in this paper. The traditional matrix converter is a buck converter with a maximum voltage transmission ratio of only 0.866, which limits the performance of the driven motor. Therefore, in this paper a quasi-Z source circuit is added to the input side of the two-stage matrix converter (TSMC) and its working principle has also been verified. In addition, the controller of the speed loop and current loop in the conventional vector control of a PMSM is a PID controller. The PID controller has the problem since its parameters are difficult to adjust and its anti-interference capability is limited. As a result, a port controlled dissipative Hamiltonian model (PCHD) of a PMSM is established. Thereafter a passivity-based controller based on the interconnection and damping assignment (IDA) of a QZMC-PMSM is designed, and the stability of the equilibrium point is theoretically verified. Simulation and experimental results show that the designed PBC control system of a PMSM based on a QZMC can make the PMSM run stably at the rated speed. In addition, the system has strong robustness, as well as good dynamic and static performances.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.28 no.11
• /
• pp.84-92
• /
• 2014

In this paper, we propose a three-phase isolated electrolytic capacitorless charger available for quick charger. In the proposed charger, electrolytic capacitor in DC link is eliminated by direct conversion from AC input to DC output. Conventional chargers are two stage structure including AC-DC and DC-DC converters, but the proposed charger can be simplified into single stage converter by using a matrix converter. And the waveform of input currents is improved by giving the weighting factor to the duty ratio of auxiliary switches. In order to verify the effectiveness of the proposed charger, simulations are carried out and a 1.2kW charger was constructed and experimented.

• Journal of Power Electronics
• /
• v.14 no.6
• /
• pp.1166-1177
• /
• 2014

A new type of topology with medium-frequency-transformer (MFT) isolation for medium voltage wind power generation systems is proposed in this paper. This type of converter is a high density power conversion system, with high performance features suitable for next generation wind power systems in either on-shore or off-shore applications. The proposed topology employs single-phase cascaded multi-level AC-AC converters on the grid side and three phase matrix converters on the generator side, which are interfaced by medium frequency transformers. This avoids DC-Link electrolytic capacitors and/or resonant L-C components in the power flow path thereby improving the power density and system reliability. Several configurations are given to fit different applications. The modulation and control strategy has been detailed. As two important part of the whole system, a novel single phase AC-AC converter topology with its reliable six-step switching technique and a novel symmetrical 11-segment modulation strategy for two stage matrix converter (TSMC) is proposed at the special situation of medium frequency chopping. The validity of the proposed concept has been verified by simulation results and experiment waveforms from a scaled down laboratory prototype.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.4
• /
• pp.50-59
• /
• 1998

This paper describes a 3.3V 8bit CMOS digital to analog converter (DAC) with two state current cell metrix architecture which consists of a 4 MSB and a 4 LSB current matrix stage. The symmetric two stage current cell matrix architecture allow the designed DAC to reduce hot only a complexity of decoding logics, but also a number of wider swing cascode curent mirros. The designed DAC with an active chip area of 0.8 mm$_{2}$ is fabricated by a 0.8 .mu.m CMOS n-well standard digital process. The experimental data shows that the rise/fall time, the settling time, and INL/DNL are6ns, 15ns, and a less than .+-.0.8/.+-.0.75 LB, respectively. The designed DAC is fully operational for the power supply down to 2.0V, such that the DAC is suitable for a low voltage and a low power system application. The power dissipation of the DAC with a single power supply of 3.3V is measured to be 34.5mW.

• Journal of Power Electronics
• /
• v.11 no.1
• /
• pp.37-44
• /
• 2011

In this paper, a four-phase 8/6-pole 4-kW SR motor drive model is presented. Based on experimental data, the model allows an accurate simulation of a drive in dynamic operation. Simulations are performed and a laboratory type set-up is built based on a TI TMS320F2812 platform to experimentally verify the theoretical results obtained for a SR motor. To reduce acoustic noise and to correct the power factor of this drive, a two-stage power converter is proposed that uses a current source rectifier (CSR) as the input stage for the asymmetrical converter of the studied SRM. Employing the space-vector modulation (SVM) method in matrix converters, the CSR switching allows the dc link's capacitors to be eliminated and the power factor of the SRM drive to be improved. As the electrical motive force (emf) is directly proportional to the rotor speed, the input voltage to the machine can be programmed to be a function of the speed with the modulation index of the CSR, leading to a reduction in the acoustic noise of the SRM drive. Simulation of the whole SRM drive system is performed using MATLAB-Simulink. The results fully comply with the required conditions such as power factor correction with an improvement in the THD.