• Journal of the Korea Institute of Information Security & Cryptology
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• v.6 no.4
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• pp.3-38
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• 1996

The mobile station shall convolutionally encode the data transmitted on the reverse traffic channel and the access channel prior to interleaving. Code symbols output from the convolutional encoder are repeated before being interleaved except the 9600 bps data rate. All the symbols are then interleaved, 64-ary orthogonal modulation, direct-sequence spreading, quadrature spreading, baseband filtering and QPSK transmission. The sync, paging, and forward traffic channel except the pilot channel in the forward CDMA channel are convolutionally encoded, block interleaved, spread with Walsh function at a fixed chip rate of 1.2288 Mcps to provide orthogonal channelization among all code channels. Following the spreading operation, the I and Q impulses are applied to respective baseband filters. After that, these impulses shall be transmitted by QPSK. Authentication in the CDMA system is the process for confirming the identity of the mobile station by exchanging information between a mobile station and the base station. The authentication scheme is to generate a 18-bit hash code from the 152-bit message length appended with 24-bit or 40-bit padding. Several techniques are proposed for the authentication data computation in this paper. To protect sensitive subscriber information, it shall be required enciphering ceratin fields of selected traffic channel signaling messages. The message encryption can be accomplished in two ways, i.e., external encryption and internal encryption.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2000.11a
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• pp.229-232
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• 2000

This research aims at developing a low-cost PC-NC system based on one-CPU and investigating the feasibility of its application to a simple-function lathe. Its hardware consists a two axes motion control board including a 24bit counter, 8253 timer, a 12bit DA converter, DIO board for PLC operation and a PC with Intel Pentium 466MHz. The fundamental real-time MC functions such as G-code interpretation, interpolation, position and velocity control of axes are performed. User programming interface with functions of icon manipulation, tool-path simulation and NC-code generation was implemented. In order to achieve real-time control and safety, axis control, NC interpretation, interpolation and user communication are completely executed during every interrupt interval of I msec.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.4
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• pp.127-135
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• 1994

In this paper we propose an EWLD(Enhanced Weighted Levenshtein Distance) algorithm to organize code-string pattern matching linear array processor based on the mappting to an one-dimensional array from a two-dimensional matching matrix, and design a processing element(PE) of the processor, N PEs are required instead of NS02T in the processor because of the mapping. Data input and output between PEs and all internal operations of each PE are performed in bit-serial fashion. The bit-serial operation consists of the computing of word distance (WD) by comparison and the selection of optimal code transformation path, and takes 22 clocks as a cycle. The layout of a PE is designed based on the double metal $1.5\mu$m CMOS rule. About 1,800 transistors consistute a processing element and 2 PEs are integrated on a 3mm$\times$3mm sized chip.

• Progress in Superconductivity
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• v.9 no.2
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• pp.157-161
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• 2008

Due to high speed operations and ultra low power consumptions RSFQ logic circuit is a very good candidate for future electronic device. The focus of the RSFQ circuit development has been on the advancement of analog-to-digital converters and microprocessors. Recent works on RSFQ ALU development showed the successful operation of an 1-bit block of ALU at 40 GHz. Recently, the study of an RSFQ analog-to-digital converter has been extended to the development of a single chip RF digital receiver. Compared to the voltage logic circuits, RSFQ circuits operate based on the pulse logic. This naturally leads the circuit structure of RSFQ circuit to be pipelined. Delay time on each pipelined stage determines the ultimate operating speed of the circuit. In simulations, a two junction Josephson transmission line's delay time was about 10 ps, a splitter's 14.5 ps, a switch's 13 ps, a half adder's 67 ps. Optimization of the 4-bit ALU circuit has been made with delay time consideration to operate comfortably at 10 GHz or above.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1559-1562
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• 2002

This paper describes a 0.13um ultra-high speed 1Mb CMOS SRAM macro with 1.7ns access time. It achieves ultra-high speed operation using two novel approaches. First, it uses process insensitive sense amplifier (Double-Equalized Sense Amplifier) which improves voltage offset by about 10 percent. Secondly, it uses new replica-based sense amplifier driver which improves bit- line evaluation time by about 10 percent compared to the conventional technique. The various memory macros can be generated automatically by using a compiler, word-bit size from 64kb to 1 Mb including repairable redundancy circuits.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.315-319
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• 2011

A switched-capacitor cyclic DAC scheme with mismatch compensation of capacitors is designed. In cyclic DAC, a little error between two capacitors is accumulated every cycle. As a result, the accumulated error influences the final analog output which is wrong data. Therefore, a mismatch compensation technique was proposed and the error can be effectively reduced, which alleviates the matching requirement. In order to verify the operation of the proposed DAC, an 8-bit switched-capacitor cyclic DAC is designed through HSPICE simulation and implemented through magna 0.18um standard CMOS process.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.1
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• pp.24-30
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• 2006

The Controller Area Network (CAN) is being widely used for real-time control application and small-scale distributed computer controller systems. When the stuff bits are generated by bit-stuffing mechanism in the CAN network, it causes jitter including variations in response time and delay In order to eliminate this jitter, stuff bits must be controlled to minimize the response time and to reduce the variation of data transmission time. This paper proposes the method to reduce the stuff bits by restriction of available identifier and bit mask using exclusive OR operation. This da manipulation method are pretty useful to the real-time control strategy with respect to performance. However, the CAN may exhibit unfair behavior under heavy traffic conditions. When there are both high and low priority messages ready for transmission, the proposed precedence priority filtering method allows one low priority message to be exchanged between any two adjacent higher priority messages. In this way, the length of each transmission delays is upper bounded. These procedures are implemented as local controllers for the ISHURO(Inha Semvung Humanoid Robot).

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.141-148
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• 2012

A design of a 32-bit fourth-stage decimation filter decimation filter used in sigma-delta analog-to-digital (A/D) converter is proposed in this work. A four-stage decimation filter with down-sampling factor of 512 and 32-bit output is developed. A multi-stage cascaded integrator-comb (CIC) filter, which reduces the sampling rate by 64, is used in the first stage. Three half-band FIR filters are used after the CIC filter, each of which reduces the sampling rate by two. The pipeline structure is applied in the CIC filter to reduce the power consumption of the CIC. The Canonic Signed Digit (CSD) arithmetic is used to optimize the multiplier structure of the FIR filter. This filter is implemented based on a semi-custom design flow and a 130nm CMOS standard cell library. This decimation filter operates at 98.304 MHz and provides 32-bit output data at an audio frequency of 192 kHz with power consumption of $697{\mu}W$. In comparison to the previous work, this design shows a higher performance in resolution, operation frequency and decimation factor with lower power consumption and small logic utilization.

• Journal of Institute of Control, Robotics and Systems
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• v.2 no.4
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• pp.337-343
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• 1996

In this paper, we investigate the defect detection by making use of pre-made reference image data and classify the defects by using the artificial neural network. The approach is composed of three main parts. The first step consists of a proper generation of two reference image data by using a low level morphological technique. The second step proceeds by performing three times logical bit operations between two ready-made reference images and just captured image to be tested. This results in defects image only. In the third step, by extracting four features from each detected defect, followed by assigning them into the input nodes of an already trained artificial neural network we can obtain a defect class corresponding to the features. All of the image data are formed in a bit level for the reduction of data size as well as time saving. Experimental results show that proposed algorithms are found to be effective for flexible defect detection, robust classification, and high speed process by adopting a simple logic operation.

• Journal of Biosystems Engineering
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• v.15 no.2
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• pp.134-142
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• 1990

This study was carried out for the development of greenhouse temperature control system by modifying an APPLE-II microcomputer attached with several interface systems. The interface systems are composed of 12 bit A/D converter, output port, multiplexer, time clock, etc. Under the operation of developed system, the greenhouse temperature was to be manipulated within the setting temperatures assumed to be appropriate for certain plant growth. The temperature control equimpents installed in the greenhouse are one-speed propeller type fan and two-phase electric heater, which are selectively started or stopped according to the control logic programmed in the control system. The results are summarized as follows : 1. The difference between two temperatures measured by the developed system and the self-recording thermometer calibrated with standard thermometer was less than $1^{\circ}C$. 2. When the temperature were measurd by 12 bit A/D converter and both electric heater and ventilation fan were controlled by developed ON/OFF logic, greenhouse temperature showed narrow fluctuation bands of less than $1^{\circ}C$ near the setting temperatures. 3. The temperature acquisition and control system developed in this study is expected to be applicable to environment control system such as greenhouse only by modifying the logic based on long term experimental data. 4. In order to reduce the measurement error and to increase the system control efficiency, it is recommended that continuous study should be carried out in the aspect of eliminating various systematic noises and improving the environmental control logic.