• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.795-803
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• 2017

This paper describes a dual-standard cryptographic processor that efficiently integrates two block ciphers ARIA and AES into a unified hardware. The ARIA-AES crypto-processor was designed to support 128-b and 256-b key sizes, as well as four modes of operation including ECB, CBC, OFB, and CTR. Based on the common characteristics of ARIA and AES algorithms, our design was optimized by sharing hardware resources in substitution layer and in diffusion layer. It has on-the-fly key scheduler to process consecutive blocks of plaintext/ciphertext without reloading key. The ARIA-AES crypto-processor that was implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,658 gate equivalents (GEs), and it can operate up to 95 MHz clock frequency. The estimated throughputs at 80 MHz clock frequency are 787 Mbps, 602 Mbps for ARIA with key size of 128-b, 256-b, respectively. In AES mode, it has throughputs of 930 Mbps, 682 Mbps for key size of 128-b, 256-b, respectively. The dual-standard crypto-processor was verified by FPGA implementation using Virtex5 device.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.50-57
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• 2009

This paper proposes a VLSI architecture of CAVLC hardware decoder which is a tool eliminating statistical redundancy in H.264/AVC video compression. The previous CAVLC hardware decoder used four stages to decode five code symbols. The previous CAVLC hardware architectures decreased decoding performance because there was an unnecessary idle cycle in between state transitions. Likewise, the computation of valid bit length includes an unnecessary idle cycle. This paper proposes hardware architecture to eliminate the idle cycle efficiently. Two methods are applied to the architecture. One is a method which eliminates an unnecessary things of buffers storing decoded codes and then makes efficient pipeline architecture. The other one is a shifter control to simplify operations and controls in the process of calculating valid bit length. The experimental result shows that the proposed architecture needs only 89 cycle in average for one macroblock decoding. This architecture improves the performance by about 29% than previous designs. The synthesis result shows that the design achieves the maximum operating frequency at 140Mhz and the hardware cost is about 11.5K under a 0.18um CMOS process. Comparing with the previous design, it can achieve low-power operation because this design is implemented with high throughputs and low gate count.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.378-386
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• 2017

A return-to-zero (RZ) digital-to-analog converter (DAC) with a tri-state switching scheme is proposed in this paper. The proposed scheme provides a triple weight output for RZ operation by using a conventional differential current switch and simple pseudo-differential F/Fs. The RZ function is realized with only two additional transistors in each F/F cell, which results in a power dissipation increase of less than 5%. To verify the performance of the proposed method, a 10-bit RZ DAC is fabricated using standard 180-nm CMOS technology. Measured results show that the worst SFDR performances are 60 dBc and 55 dBc in the 1st and 2nd Nyquist bands, respectively, when operating at 650 MHz clock frequency. The total power consumption is 64 mW, and the active area occupies $0.25mm^2$.

• The Transactions of the Korea Information Processing Society
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• v.3 no.4
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• pp.961-968
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• 1996

In the frame of Koreasat Project, it has been identified the task to implement a pilot satellite network module to provide LAN-to-LAn in ground system for satellite links. The pilot network will support an experiment to verify the performances of the considered applications through a satellite.This paper proposes a satellite-LAN interconnecting architecture making full use of satellite benefits and counteracting satellite demerits. The architectureprovides high quality data transmission and high perfrmance for satellite bit errors by using a connection- oriented satellite protocol which can establish multiple logical links between two nodes. As a protocol conversion method, router-type interconnection was selected to guard against problems. Based on this architecture, a satellite LAN interconnecting system has been designed, which includes a 1.8 meter antenna with a 4 watt transceiver, a satellite modem and the developed satellite network interface. The system can support high speed transmission rates of up to 1.544 Mbs and superior network management as well.

• Journal of KIISE:Software and Applications
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• v.37 no.11
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• pp.851-858
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• 2010

Most mobile devices use a NAND flash memory as their secondary memory. A compressed code of the firmware is stored in the NAND flash memory of mobile devices in order to reduce the size and the loading time of the firmware from the NAND flash memory to a main memory. In order to use a demand paging properly, a compressed code should be decompressed very quickly. The thesis introduces a new dictionary based compression algorithm for the fast decompression. The introduced compression algorithm uses a different method with the current LZ method by storing the "exclusive or" value of the two instructions when the instruction for compression is not equal to the referenced instruction. Therefore, the thesis introduces a new compression format that minimizes the bit operation in order to improve the speed of decompression. The experimental results show that the decoding time is reduced up to 5 times and the compression ratio is improved up to 4% compared to the zlib. Moreover, the proposed compression method with the fast decoding time leads to 10-20% speed up of booting time compared to the booting time of the uncompressed method.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.157-165
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• 2013

In this paper, efficient digit-serial VLSI architecture for 1D (9,7) lifting-based discrete wavelet transform (DWT) filter has been proposed. The proposed architecture computes the DWT in digit basis, so that the required hardware is reduced. Also, the multiplication is replaced with the shift and add operation to minimize the hardware requirement. Bit allocation for input, output, and the internal data has been determined by analyzing the PSNR. We have carefully designed the data feedback latency not to degrade the performance in the recursive folded scheduling. The proposed digit-serial architecture requires small amount of hardware but achieve 100% of hardware utilization, so we try to optimize the tradeoffs between the hardware cost and the performance. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a DongbuHitek $0.18{\mu}m$ STD cell library. The maximum operating frequency is 330MHz with 3,770 gates in equivalent two input NAND gates.

• The KIPS Transactions:PartA
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• v.9A no.2
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• pp.259-266
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• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM (or SRAM) cell. Layout pitch of one-bit-wide logic is Identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1) simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.5
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• pp.7-16
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• 2000

This paper described a design and implementation of the division/square-root for a redundant floating point binary number using high-speed quotient selector. This division/square-root used the method of a redundant binary addition with 25MHz clock speed. The addition of two numbers can be performed in a constant time independent of the word length since carry propagation can be eliminated. We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in each iterative step. It performed the division and square-toot by a redundant binary addition to the shifted binary number every 16 cycles. Also the circuit uses the nonrestoring method to obtain a quotient. The quotient selection logic used a leading three digits of partial remainders in order to be implemented in a simple circuit. As a result, the performance of the proposed scheme is further enhanced in the speed of operation process by applying new quotient selection addition logic which can be parallelly process the quotient decision field. It showed the speed-up of 13% faster than previously presented schemes used the same algorithms.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.4
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• pp.1903-1907
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• 2013

Heart condition should be observed for long periods of time because it does not appear abnormal all the time. However, there are many difficulties checking our health for a long time due to its size, operation of equipment, and cost. To solve these problems, an electrocardiograms(ECG), specially interfacing three gel-less metal electrodes for low cost portable applications, is designed and implemented. Gel-less metal electrodes are used for ECG monitoring system instead of gel-type electrodes that can cause skin rashes and itching problem. The whole ECG system consists of two parts-analog and digital circuits. The analog measurement circuit that has a 18*25mm size is made up of op-amps maintaining a sufficiently high common-mode noise rejection and passive elements of SMD type. Analog heart signal is converted to digital stream suitable for display on a TFT-LCD by an 8-bit microcontroller. The size of the completed ECG system is 25*80*50mm and its weighing is about 150g, which is small enough to be easily used. Therefore, the implemented ECG system can be used as a portable one.

• Journal of Biosystems Engineering
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• v.37 no.6
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• pp.352-358
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• 2012

Purpose: The inexpensive black box system was developed to acquire and save driving information, to give the slope information, and to transmit SOS and theft signal. Method: The device consists of a main micro controller to acquire and save data, a GPS sensor module, a CDMA module, a touch LCD module, a RF (Radio Frequency) ID module, a SD (Secure Digital) card module, an emergency electric power source, a theftproof circuit, and a sensing device. The sensing device consists of a 8 bit micro controller, a accelerometer to detect impulse, two slope sensors to detect roll and pitch angle and a circuit to detect operation of 6 lighting devices. Results: Test results are as follows: 1) a tractor can be start up only with an electronic key (password or RFID card), 2) theft signal was transmitted when a tractor moved without an electronic key, 3) SOS was transmitted at conditions that rollover or crash happened. 4) 5 more than per 1s data are recorded at 5 minute intervals as new file name in SD card. Conclusions: This system can be used to save travelling record, reduce accident, prevent theft and rescue life in the accidents.