• 제목/요약/키워드: Tunneling barrier layer

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SiO2/Si3N4 터널 절연악의 적층구조에 따른 비휘발성 메모리 소자의 특성 고찰 (Study of Nonvolatile Memory Device with SiO2/Si3N4 Stacked Tunneling Oxide)

  • 조원주
    • 한국전기전자재료학회논문지
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    • 제22권1호
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    • pp.17-21
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    • 2009
  • The electrical characteristics of band-gap engineered tunneling barriers consisting of thin $SiO_2$ and $Si_3N_4$ dielectric layers were investigated for nonvolatile memory device applications. The band structure of band-gap engineered tunneling barriers was studied and the effectiveness of these tunneling barriers was compared with the conventional tunneling $SiO_2$ barrier. The band-gap engineered tunneling barriers composed of thin $SiO_2$ and $Si_3N_4$ layers showed a lower operation voltage, faster speed and longer retention time than the conventional $SiO_2$ tunnel barrier. The thickness of each $SiO_2$ and $Si_3N_4$ layer was optimized to improve the performance of non-volatile memory.

Polyimide 터널 장벽을 이용한 Arachidicacid 단분자막의 비탄성 터널 스펙트라 (Inelastic Electron Tunneling Spectroscopy of 1-layer Arachidicacid films using a Polyimide barrier)

  • 이원재;강도열;암본광정
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1994년도 추계학술대회 논문집 학회본부
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    • pp.234-236
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    • 1994
  • We fabricated Au/PI/Pb and Au/PI/1-layer Arachidic acid/Pb structures in order to electron transport properties through the junctions. It was found that 9-layer PI LB films function as a good tunneling barrier from the I-V properties. And several peaks originating in the vibrational modes of the constituent molecules of 1-layer arachidicacid LB films were clearly observed in $d^2V/dI^2-V$ curves.

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Au/Polyimide/유기 단분자막/Pb 구조의 IETS (IETS of Au/Polyimide/1-layer organic film /Pb Structures)

  • 이원재;최명규;강도열
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1995년도 춘계학술대회 논문집
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    • pp.230-233
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    • 1995
  • Using Polyimide Langmuir-Blodgett(LB) films as a tunneling barrier, Current -Voltage(I-V) characteristics and inelastic electron tunneling spectroscoupy(IETS) of the junctions incorporating 1-layer orgainc monolayer were invesgated. Several peaks originating in vibrational modes of constituted molecules of 1-layer monolayers were clearly observed in the IET spectra.

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Engineered tunnel barrier가 적용되고 전화포획층으로 $HfO_2$를 가진 비휘발성 메모리 소자의 특성 향상 (Enhancement of nonvolatile memory of performance using CRESTED tunneling barrier and high-k charge trap/bloking oxide layers)

  • 박군호;유희욱;오세만;김민수;정종완;이영희;정홍배;조원주
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2009년도 하계학술대회 논문집
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    • pp.415-416
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    • 2009
  • The tunnel barrier engineered charge trap flash (TBE-CTF) non-volatile memory using CRESTED tunneling barrier was fabricated by stacking thin $Si_3N_4$ and $SiO_2$ dielectric layers. Moreover, high-k based $HfO_2$ charge trap layer and $Al_2O_3$ blocking layer were used for further improvement of the NVM (non-volatile memory) performances. The programming/erasing speed, endurance and data retention of TBE-CTF memory was evaluated.

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$SrTiO_3$ 장벽층을 이용한 경사형 모서리 접합의 터널링 자기저항 특성연구 (Tunneling Magnetoresistance of a Ramp Edge Junction with $SrTiO_3$ Barrier Layer)

  • Lee, Sang-Suk;Kim, Young-Il;Hwang, Do-Guwn;Kim, Sun-Wook;Kungwon Rhie;Rhee, Jang-Roh
    • 한국자기학회:학술대회 개요집
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    • 한국자기학회 2002년도 동계연구발표회 논문개요집
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    • pp.174-175
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    • 2002
  • A ramp-type tunneling magnetoresistance (TMR) junction having structure NiO(60 nm)/pinned Co(10 nm)MiO(60 nm)/barrier SrTiO$_3$(2-10 nm)/free NiFe(10 nm) with the 15 degree slope was investigated. We obtained nonlinear I(V) characteristics for ramp-type tunneling junctions that have distinctive difference with and without applied magnetic field. In the barrier SrTiO$_3$ thickness of 4 nm, the TMR was about 52% at a bias voltage of 50 mV. (omitted)

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비휘발성 메모리 적용을 위한 $SiO_2/ZrO_2$ 다층 유전막의 전기적 특성 (Electrical characteristic of stacked $SiO_2/ZrO_2$ for nonvolatile memory application as gate dielectric)

  • 박군호;김관수;오준석;정종완;조원주
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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    • pp.134-135
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    • 2008
  • Ultra-thin $SiO_2/ZrO_2$ dielectrics were deposited by atomic layer chemical vapor deposition (ALCVD) method for non-volatile memory application. Metal-oxide-semiconductor (MOS) capacitors were fabricated by stacking ultra-thin $SiO_2$ and $ZrO_2$ dielectrics. It is found that the tunneling current through the stacked dielectric at the high voltage is lager than that through the conventional silicon oxide barrier. On the other hand, the tunneling leakage current at low voltages is suppressed. Therefore, the use of ultra-thin $SiO_2/ZrO_2$ dielectrics as a tunneling barrier is promising for the future high integrated non-volatile memory.

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Polyimide 터널 장벽을 이용한 Au/polyimide/유기 단분자막/Pb 구조에서 비탄성 전자 터널링에 관한 연구 (Inelastic Electron Tunneling in Au/polyimide/monolayer Organic Film/Pb Structures using a Polyimide Barrier)

  • 이호식;이원재;장경욱;최명규;이성일;김태완;;이준웅
    • 한국전기전자재료학회논문지
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    • 제17권2호
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    • pp.196-200
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    • 2004
  • Using polyimide Langmuir-Blodgett(LB) films as a tunneling harrier, we fabricated Au/Polyimide/1-layer arachidic acid/Pb structure in order to investigate electron transport properties through a junction. It was found that 9-layer polyimide LB films function as a good tunneling harrier in a study of current-voltage(I-V) chararteristics. And several peaks originating in the vibrational modes of the constituent molecules of 1-layer arachidic acid LB films were clearly observed in d$^2$V/dI$^2$- V corves.

버퍼층과 음전극에 따른 유기 발광 소자의 전기적 특성과 발광 효율 (Electrical Properties and Luminous Efficiency in Organic Light-Emitting Diodes Depending on Buffer Layer and Cathodes)

  • 정동회;김상걸;홍진웅;이준웅;김태완
    • 한국전기전자재료학회논문지
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    • 제16권5호
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    • pp.409-417
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    • 2003
  • We have studied electrical properties and luminous efficiency of organic light-emitting diodes(OLEDs) with different buffer layer and cathodes in a temperature range of 10 K and 300 K. Four different device structures were made. The OLEDs are based on the molecular compounds, N,N'-diphenyl-N,N'-bis(3-methylphenyl)-1,1'-biphenyl-4,4'-diamine (TPD) as a hole transport, tris(8-hydroxyquinolinato) aluminum(III) (Alq$_3$) as an electron transport and omissive layer, and poly(3,4-ethylenedioxythiophene) :poly (styrenesulfonate) (PEDOT:PSS ) as a buffer layer. And LiAl was used as a cathode. Among the devices, the ITO/PEDOT:PSS/TPD/Alq$_3$/LiAl structure has a low energy-barrier height for charge injection and show a good luminous efficiency. We have got a highly efficient and low-voltage operating device using the conductive PEDOT:PSS and low work-function LiAl. From current-voltage characteristics with temperature variation, conduction mechanisms are explained SCLC (space charge limited current) and tunneling one. We have also studied energy barrier height and luminous efficiency at various temperature.

부도체층 제작조건에 따른 강자성 터널접합의 투과자기저항 특성 연구 (Tunneling magnetoresistance in ferromagnetic tunnel junctions with conditions of insulating barrier preparation)

  • 백주열;현준원
    • 한국표면공학회지
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    • 제32권1호
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    • pp.61-66
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    • 1999
  • The Spin-dependent tunneling magnetoresistance (TMR) effect was observed in $NiFe/Al_2O_3$/Co thin films. The samples were prepared by magnetron sputtering in a system with a base pressure of $3\times10^{-6}$Torr. the insulating $Al_2O_3$layer was prepared by r.f. plasma oxydation method of a metallic Al layer. The ferromagnetic and insulating layers were deposited through metallic masks to produce the cross pattern form. The junction has an active area of $0.3\times0.3\textrm{mm}^2$ and the $Al_2O_3$layer is deposited through a circular mask with a diameter of 1mm. It is very important that insulating layer is formed very thinly and uniformly in tunneling junction. The ferromagnetic layer was fabricated in optimum conditions and the surface of that was very flat, which was observed by AFM. Tunneling junction was confirmed through nonlinear I-V curve. $NiFe/Al_2O_3$/Co junction was observed for magnetization behavior and magnetoresistance property and magnetoresistance property is dependent on magnetization behavior and magnetoresistance property and magnetoresistance property is dependent on magnetization behavior of t재 ferromagnetic layer. The maximum magnetoresistance ratio was about 6.5%.

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비휘발성 메모리를 위한 $SiO_2/Si_3N_4$ 적층 구조를 갖는 터널링 절연막의 열처리 효과 (Annealing Effects of Tunneling Dielectrics Stacked $SiO_2/Si_3N_4$ Layers for Non-volatile Memory)

  • 김민수;정명호;김관수;박군호;정종완;정홍배;조원주
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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    • pp.128-129
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    • 2008
  • The annealing effects of $SiO_2/Si_3N_4$ stacked tunneling dielectrics were investigated. I-V characteristics of band gap engineered tunneling gate stacks consisted of $Si_3N_4/SiO_2/Si_3N_4$(NON), $SiO_2/Si_3N_4/SiO_2$(ONO) dielectrics were evaluated and compared with $SiO_2$ single layer using the MOS(Metal-Oxide-Semiconductor) capacitor structure. The leakage currents of engineered tunneling barriers (ONO, NON stacks) are lower than that of the conventional $SiO_2$ single layer at low electrical field. Meanwhile, the engineered tunneling barriers have larger tunneling current at high electrical field and improved electrical characteristics by annealing processes than $SiO_2$ layer.

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