• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.4
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• pp.880-884
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• 2011

The matrix-type superconducting fault current limiter (MSFCL) consists of the trigger and current-limiting parts. The trigger part with reactors connected in parallel improves the quenching characteristics by applying the external magnetic field into the superconducting units. The current-limiting part with superconducting units connected in parallel and shunt reactors connected in series limit the fault current when the fault occurs. We developed the integrated reactor with the trigger and the current-limiting parts to apply high external magnetic field into the superconducting units. This was composed of a superconducting unit for the trigger part and two superconducting units for the current-limiting parts. We confirmed that the external magnetic field generated in the MSFCL with an integrated reactor was larger than that of the MSFCL with the separated reactors. So the differences of voltages generated between superconducting units were decreased in the difference according to the increment of the applied voltage. The whole magnitude of the SFCL was reduced because the volume of an integrated reactor could be reduced by one-third than that of the separated reactors. We confirmed that the critical behavior between the superconducting units in the MSFCL with an integrated reactor was more improved than that of the MSFCL with the separated reactors.

• Journal of IKEEE
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• v.19 no.2
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• pp.265-270
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• 2015

In this paper, we proposed a dual-directional SCR (silicon-controlled rectifier) based ESD (electrostatic discharge) protection circuit. In comparison with conventional SCR, this ESD protection circuit can provide an effective protection against ESD pulses in the two opposite directions, so the ESD protection circuit can be discharged in two opposite direction. The proposed circuit has a higher holding voltage characteristic than conventional SCR. These characteristic enable to have latch-up immunity under normal operating conditions as well as superior full chip ESD protection. it was analyzed to figure out electrical characteristics in term of individual design parameters. They are investigated by using the Synopsys TCAD simulator. In the simulation results, it has trigger voltage of 6.5V and holding voltage increased with different design parameters. The holding voltage of the proposed circuit changes from 2.1V to 6.3V and the proposed circuit has symmetrical I-V characteristic for positive and negative ESD pulse.

• Journal of IKEEE
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• v.10 no.2 s.19
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• pp.149-155
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• 2006

In this study, the design of low voltage DC-DC converter with low triggering ESD (Electro-Static Discharge) protection circuit was investigated. The purpose of this paper is design optimization for low voltage(2.5V to 5.5V input range) DC-DC converter using CMOS switch. In CMOS switch environment, a dominant loss component is not switching loss but conduction loss at 1.2MHz switching frequency. In this study a constant frequency PWM converter with synchronous rectifier is used. And zener Triggered SCR device to protect the ESD phenomenon was designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 8V.

• Journal of IKEEE
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• v.11 no.1 s.20
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• pp.54-60
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• 2007

In this study novel ESD protection device, namely, N/P-type Low Voltage Triggered SCR, has been proposed, for high speed I/O interface. Proposed device could lower high trigger voltage($\sim$20V) of conventional SCR and reduce latch-up phenomenon of protection device during the normal condition. In this Study, the proposed NPLVTSCR has been simulated using TMA MEDICI device simulator for electrical characteristic. Also the proposed device's test pattern was fabricated using 90nm TSMC's CMOS process and was measured electrical characteristic and robustness. In the result, NPLVTSCR has 3.2V $\sim$ 7.5V trigger voltage and 2.3V $\sim$ 3.2V holding voltage by changing PMOS gate length and it has about 2kV, 7.5A HBM ESD robustness(IEC61000-4-2).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.35-38
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• 2018

This paper describes a low-power MPPT interface for DC-type energy harvesting sources. The proposed circuit consists of an MPPT controller, a bias generator, and a voltage detector. The MPPT controller consists of an MPG (MPPT Pulse Generator) with a schmitt trigger, a logic gate operating according to energy type (light, heat), and a sample/hold circuit. The bias generator is designed by employing a beta multiplier structure, and the voltage detector is implemented using a bulk-driven comparator and a two-stage buffer. The proposed circuit is designed with $0.35{\mu}m$ CMOS process. The simulation results show that the designed circuit consumes less than 100nA of current at an input voltage of less than 3V and the maximum power efficiency is 99.7%. The chip area of the designed circuit is $1151{\mu}m{\times}940{\mu}m$.

• The Transactions of the Korean Institute of Power Electronics
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• v.23 no.4
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• pp.281-285
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• 2018

An isolated feedback method for measuring the inverter DC-link voltage is proposed. This method provides a simple and economical solution to inverter control systems that use a flyback converter as a controller power supply. In the proposed method, data on the DC-link voltage are acquired when the primary side voltage appears on the secondary side of the flyback transformer, thereby eliminating the need to adopt an extra signal isolation method. To solve the non-synchronization problem between the flyback converter switching and main controller sampling, the external interrupt function of the micro-controller is used as a trigger signal for the A/D conversion.

• Proceedings of the KIEE Conference
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• 1998.07f
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• pp.1869-1871
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• 1998

In this paper, we designed and fabricated a fast switching system for high power pulse. This system consists of a voltage conversion circuit, high voltage charging circuit, trigger circuit, and discharging circuit. Especially discharging line is designed by strip-line for low inductance and resistance. The experimental result is that current slew rate of the system is 6.67kA/86ns and this result is fully qualified for initiating EBW or EFI

• Journal of IKEEE
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• v.10 no.2 s.19
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• pp.141-148
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• 2006

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low signal swing range, maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD Phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, The high speed I/O interface circuit with the low triggered ESD protection device in one-chip was designed.

• Proceedings of the KIEE Conference
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• 2001.04a
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• pp.215-217
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• 2001

This paper describes an all solid-state switch pulse generator for various applications where square pulse voltage is required. The pulse generator produces various voltage pulses: voltage $5{\sim}100kV$. current $10{\sim}200A$, pulse width $1{\sim}10{\mu}sec$, repetition rate up to 500Hz. The output power is the combination of these parameters up to 10kW. It consists of a DC-DC converter and several pulse generating modules which are connected in series to obtain higher pulse voltage. Each module contains semiconductor switches (IGBT's), energy storage capacitors and control units to trigger switches. The structure and operational principle are described and the protection circuit for reliable operation is suggested. Experimental results show that the pulse generator can be used for applications with nonlinear loads.

• Proceedings of the KIEE Conference
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• 1999.07e
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• pp.2189-2191
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• 1999

To improve the reliability of the klystron-modulator systems, the stable operations of the thyratron an important factor of the system are required. The thyratron always has a possibility of self-fire according to the conditions of the applied high voltage and this induces the system fault. Therefore a command charging method was introduced to reduce the applied tim8 of the high voltage into the thyratron. The high voltage switch used in the command charging method is the SCR (1.6 kV, 50A) and consists of 10 SCRs in series to discharge 10 kV. A pulse transformer was used to apply the trigger pulse. The objectives of this research are the fabrication of the semiconductor switch and the study of the experimental result of the operation characteristics of the high voltage semiconductor switch.