• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.167-174
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• 2012

In this paper a ultrasonic oil level meter for measuring oil levels of vehicle transmissions is designed and its effectiveness is shown by experiments. On a FPGA(Field Programmable Gate Array) project IDE(Integrated Development Environment), all digital circuits for the meter is designed using a FPGA, which enables simplicity and high performance of the meter as well as short developing time. Also, power supplying circuit and analog circuits to process low voltage ultrasonic echo signal are designed and simulated. Under experiments, the designed level meter is verified to provide accuracy to within 1mm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.292-300
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• 2015

This paper proposes a high-efficiency, dual-mode PWM / linear buck converter with a wide-input range. The proposed converter was designed with a mode selector that can change the operation between PWM / linear mode by sensing a load current. The proposed converter operates in a linear mode during a light load and in PWM mode during a heavy load condition in order to ensure high efficiency. In addition, the mode selector uses a bit counter and a transmission gate designed to protect from a malfunction due to noise or a time-delay. Also, in conditions between $-40^{\circ}C$ and $140^{\circ}C$, the converter has variations in temperature of $0.5mV/^{\circ}C$ in the PWM mode and of $0.24mV/^{\circ}C$ in the linear mode. Also, to prevent malfunction and breakdown of the IC due to static electricity, the reliability of IC was improved by embedding a self-produced 8 kV-class(Chip level) ESD protection circuit of a P-substrate Triggered SCR type with high robustness characteristics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.3-4
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• 2005

Germanium nanocrystals(NCs) were formed in the silicon dioxide($SiO_2$) on Si layers by Ge implantation and rapid thermal annealing process. The density and mean size of Ge-NCs heated at $800^{\circ}C$ during 10 min were confirmed by High Resolution Transmission Electron Microscopy. Capacitance versus voltage(C-V) measurements of MOS capacitors with single $Al_2O_3$ capping layers were performed in order to study electrical properties. The C-V results exhibit large threshold voltage shift originated by charging effect in Ge-NCs, revealing the possibility that the structure is applicable to Nano Floating Gate Memory(NFGM) devices.

• Korean Journal of Optics and Photonics
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• v.8 no.6
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• pp.492-499
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• 1997

We proposed and studied an all-optical switching device made of a bent nonlinear waveguide and an all-optical logic gate made of a bent nonlinear Y-junction. The proposed devices as switch and a logic function are based on the evolution of nonlinear guided wave along a bent nonlinear waveguide. Since the characteristics of beam propagation depens on the nonlinearity, input power and bent angle of waveguide, the characteristics of output power transmission is calculated by variation the such parameters. Furthermore, by calculating the output power through the nonlinear media with different positions of detector in nonlinear media, we could find the ideal digital switching performance at specific position of detector and implement several all-optical logic functions (AND, OR, XOR) by power contrast between waveguide end and nonlinear media.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1567-1570
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• 2002

This paper deals with FPGA(Field Programmable Gate Array) implementation of the AAC(Advanced Audio Coding) decoder. On modern computer culture, according to the high quality data is required in multimedia systems area such as CD, DAT(Digital Audio Tape) and modem. So, the technology of data compression far data transmission is necessity now. MPEG(Moving Picture Experts Group) would be a standard of those technology. MPEG-2 AAC is the availableness and ITU-R advanced coding scheme far high quality audio coding. This MPEG-2 AAC audio standard allows ITU-R 'indistinguishable' quality according to at data rates of 320 Kbit/sec for five full-bandwidth channel audio signals. The compression ratio is around a factor of 1.4 better compared to MPEG Layer-III, it gets the same quality at 70％ of the titrate. In this paper, for a real time processing MPEG2 AAC decoding, it is implemented on FPGA chip. The architecture designed is composed of general DSP(Digital Signal Processor). And the Processor designed is coded using VHDL language. The verification is operated with the simulator of C language programmed and ECAD tool.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.321-334
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• 2003

Globally-Asynchronous Locally-Synchronous (GALS) systems are worthy of notice as an adequate architecture for a large scaled chip design with guaranteeing easy designs and functional confidence. In this paper, we suggest an advanced structure of the interface unit which is indispensable for GALS systems by using stoppable clocks. The proposed interface unit is composed of a sender module and a receiver module. The sender module can carry out data transmission partially without the relation to an internal clock. We have designed it with 0.25${\mu}{\textrm}{m}$ standard cell library at the gate level and simulated its operation to show performance improvement. Finally, we constructed all example circuit with the interface unit and proved the correct operation of it.

• Journal of electromagnetic engineering and science
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• v.14 no.4
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• pp.411-414
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• 2014

A switch is one of the most useful circuits for controlling the path of signal transmission. It can be added to digital circuits to create a kind of gate-level device and it can also save information into memory. In RF subsystems, a switch is used in a different way than its general role in digital circuits. The most important characteristic to consider when designing an RF switch is keeping the isolation as high as possible while also keeping insertion loss as low as possible. For high isolation, we propose leakage signal cancellation and inductive switching for designing a singlepole double-throw (SPDT) RF switch. By using the proposed method, an isolation level of more than 23 dB can be achieved. Furthermore, the heterojunction bipolar transistor (HBT) process is used in the RF switch design to keep the insertion loss low. It is demonstrated that the proposed RF switch has an insertion loss of less than 2 dB. The RF switch operates from 1 to 8 GHz based on the $0.18-{\mu}m$ SiGe HBT process, taking up an area of $0.3mm^2$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.264-267
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• 2002

This paper presents the design of a pipelined virtual output queue routing engine for an advanced input-queued ATM switch, which has a serial cross bar structure. The proposed routing engine has been designed for wire-speed routing with a pipelined buffer management. It provides the tolerance of requests and grants data transmission latency between the routing engine and central arbiter using a new request control method that is based on a high-speed shifter. The designed routing engine has been implemented in a field programmable gate array (FPGA) chip with a 77MHz operating frequency, 16$\times$16 switch size, and 2.5Gbps/port speed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.11
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• pp.1655-1662
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• 1993

In this paper we discuss three algorithms-Direct, Successive, and Recursive-on parallel CRC(Cyclic Redundancy Check) verification. The algorithms are derived by combining the byte-syndromes precomputed from the generator polynomial. These algorithms are compared in terms of the amount of hardware and the speed of operation. Since the algorithms can be generalized easily, we took the ATM cell delineation example for easier description. As an application of the algorithm Recursive, an ATM cell delineation module suitable for STM-1 transmission has been successfully realized through commercially available field programmable gate arrays.

• Journal of Biosystems Engineering
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• v.25 no.4
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• pp.257-264
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• 2000

A tractor attached TMR(model 430) mixer has been developed in a previous study. However, the mixer was found to be improved through field applications in its capacity, manufacturing cost, ergonomic design and power-train requirement. The TMR mixer was modified into a model TMR500, approved by Institute of Agricultural Mechanization, as follows : 1. Roughage cutting system was seperated from the mixer, resulting in the 33% reduction of manufacturing cost. 2. Enlarged hopper capacity enabled to feed 60 heads at a batch. 3. Hydraulically controlled gate system saved ergonomic man power. 4. Power transmission system was changed from a chain-sprocket system(27:1) to the gear-train reduction system(38.6:1) to satisfy the recommended use of 540rpm PTO input.