• Title/Summary/Keyword: Transmission Gate

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Design and Performance Evaluation of RS Codec for DTMF Modulation in Mobile Radio Channels (이동무선 채널에서 DTMF 변조 방식에 대한 RS 복부호기의 설계 및 성능평가)

  • 송문규;이상설;김우현
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.2 no.1
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    • pp.133-140
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    • 1998
  • In this paper, RS coded DTMF modulation for reliable data transmission over mobile fading channels is considered. The circuits of (15,9) RS codec are proposed and synthesized, and the performances are evaluated over fading channels. The codec circuits take about 14000 gates standardized by 2-input NAMD gate. The (15,9) RS coded DTMF signalling provides theoretical coding gain more than 20 dB over fading channels for BER 10.6, the criterion for data transmissions in mobile communications such as IMT-2000. Thus, It is very effective to apply RS codec to DTMF signalling for data transmission in mobile communications over fading channels.

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Design and Implementation of Multi-channel FFT Processor for MIMO Systems (MIMO 시스템을 위한 다채널 FFT 프로세서의 설계 및 구현)

  • Jung, Yongchul;Cho, Jaechan;Jung, Yunho
    • Journal of Advanced Navigation Technology
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    • v.21 no.6
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    • pp.659-665
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    • 2017
  • In this paper, a low complexity fast Fourier transform(FFT) processor is proposed for multiple input multiple output(MIMO) systems. The IEEE 802.11ac standard has been adopted along with the demand for a system capable of high channel capacity and Gbps transmission in order to utilize various multimedia services using a wireless LAN. The proposed scalable FFT processor can support the variable length of 64, 128, 256, and 512 for 8x8 antenna configuration as specified in IEEE 802.11ac standard with MIMO-OFDM scheme. By reducing the required number of non-trivial multipliers with mixed-radix(MR) and multipath delay commutator(MDC) architecture, the complexity of the proposed FFT processor was dramatically decreased. Implementation results show that the proposed FFT processor can reduced the logic gate count by 50%, compared with the radix-2 SDF FFT processor. Also, compared with the 8-channel MR-2/2/2/4/2/4/2 MDC processor and 8-channel MR-2/2/2/8/8 MDC processor, it is shown that the gate count is reduced by 18% and 17% respectively.

A Design of Bandwidth Allocation Scheme with Priority Consideration for Upstream Channel of Ethernet PON (Ethernet PON에서 서비스 클래스별 우선 순위를 고려한 상향 채널 대역 할당 기법)

  • 이호숙;유태환;문지현;이형호
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.11A
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    • pp.859-866
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    • 2003
  • In this paper, we designed the bandwidth allocation scheme with priority consideration for upstream channel access of EthernetPON. The objective of our scheme is to control the multi services in more effective way according to their CoS(Class of Service) or QoS(Quality of Service). The designed scheme considers transmission priority in the both side of OLT and ONU. In the OLT's view, the Two-step scheduling algorithm is applied with which we can support multiple bandwidth allocation policies simultaneously, i.e. SBA for the time-sensitive, constant rate transmission services and DBA for the best-effort services. This Two-step scheduling algorithm reduces the scheduling complexity by separating the process of transmission start time decision from the process of grant generation. In the ONU's view, the proposed scheme controls 8 priority queues of the 802.1d recommended 8 service classes. Higher priority queue is serviced in prior during the allowed GATE time from OLT. The OPNET modeling and simulation result compares the performance of each bandwidth allocation policy with SBA or DBA only approach.

Rapid Implementation of the MAC and Interface Circuits fot the Wireless LAN Cards Using FPGA

  • Jiang, Songchar
    • Journal of Communications and Networks
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    • v.1 no.3
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    • pp.201-212
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    • 1999
  • This paper studies the rapid design and implementation of the medium access control(MAC) and related interface circuits for 802.11 wireless LANs based on the field programmed gate ar-ray(FPGA) technology. Our design is thus aimed to support both the distributed coordination function (DCF) and the point coordination function(PCF) with the aid of FPGA technology. Further-more, in an infrastructure network, some stations may serve as the access points (APs) which may function like a learning bridge. This paper will also discuss how to design for such application. The hardware of the MAC and interface may at least consist of three major parts: wireless transmission and reception processes and in-terface, host(bus) interface, and the interface to the distributed system (optional). Through the increasing popularity of FPGA de-sign, this paper presents how Complex Programmable Logic De-vices(CPLD) can be utilized for speedy design of prototypes. It also demonstrates that there is much room for low-cost hardware prototype design to accelerate the processing speed of the MAC control function and for field testing.

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A Study on the Change in Production Costs and Electricity Tariffs with the Introduction of Renewable Portfolio Standard (RPS(Renewable Portfolio Standard) 제도 도입을 고려한 전기요금변화에 관한 연구)

  • Hong, Hee-Jung;Han, Soek-Man;Kim, Bal-Ho
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.58 no.4
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    • pp.708-717
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    • 2009
  • Recently, Korea government decided to introduce RPS (Renewable Portfolio Standard) mechanism which requires electricity providers to gradually increase the amount of renewable energy sources such as wind, solar, bioenergy, and geothermal. As a consequence, it is expected that the long-term fuel mix would be changed to result in more expensive production and the increased production costs would be distributed to the rate payers via electricity tariffs. This paper presents the change in long-term fuel mix in year 2020 with the four RPS scenarios of 3%, 5%, 10% and 20%, and the methodologies for collecting the increased production costs through new tariff schedule. The studies on long-term fuel mix have been carried out with the GATE-PRO (Generation And Transmission Expansion Program) optimization package, a mixed-integer program developed by the Korea Energy Economics Institute and Hongik university. Three methodologies for distributing the production costs to the rate payers have also been demonstrated.

A Study on the Optimal Fuel Mix for the Introduction of RPS(Renewable Portfolio Standard) (RPS 도입을 고려한 최적 전원구성에 관한 연구)

  • Lee, Jeong-In;Kang, Dong-Ju;Kim, Gwang-Mo;Kim, Bal-Ho
    • Proceedings of the KIEE Conference
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    • 2008.11a
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    • pp.426-428
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    • 2008
  • 현재 우리는 화석연료의 고갈 및 에너지 수입 해외의존도의 심화, 최근의 고유가 등으로 신재생에너지원의 개발 및 이용, 보급 확대가 국가적 관심사항이 되고 있으며, 신재생에너지를 전원을 보급하기 위해 노력하고 있다. 정부는 2012년부터 RPS(Renewable Portfolio Standard)를 도입하여 신재생에너지전원의 비중을 설비용량의 5%(발전량의 7%)까지 확대하는 것을 목표로 하고 있다. 따라서 본 연구에서는 가격규제가 아닌, 보급목표를 규제하여 시장에서 가격이 결정되는 RPS를 도입하였을 경우의 현 전력수급계획의 수립절차에 대한 상세한 고찰과 문제점 분석을 통해 우리나라의 RPS를 반영한 최적 전원구성비를 도출하기 위한 방안을 GATE-PRO(Generation And Transmission Expansion PROgram) 모형을 이용하여 모색하고자 한다. 또한 이를통해 우리나라의 RPS도입이 전력수급계획에 미치는 영향을 살펴보고자 한다.

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A Study on a Charge-Change According to the Introduction of RPS(Renewable Portfolio Standard) (RPS 재도 도입에 따른 전기요금 변화에 관한 연구)

  • Hong, Hee-Jung;Kim, Gwang-Mo;Kim, Gang-Won;Han, Seok-Man;Kim, Bal-Ho
    • Proceedings of the KIEE Conference
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    • 2008.11a
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    • pp.429-431
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    • 2008
  • 기후변화협약 체결 당시 개발도상국으로 분류되어 있던 우리나라는 현재 온실가스 감축의무를 부담하지 않고 있으나, 우리나라의 CO2 배출량 및 배출량 증가율을 고려해 볼 때, 제2차 공약기간(2012년$\sim$2016년) 동안의 온실가스 감축의무 부담이 예견되고 있다. 온실가스 감축의무를 이행하기 위하여 정부는 2012년부터 RPS(Renewable Portfolio Standard) 제도를 도입을 고려하고 있다. 신재생에너지전원의 비중을 설비용량의 5%(발전량의 7%)까지 확대를 예상하여, 본 연구에서는 RPS 제도를 도입을 고려할 때 전원구성의 변화를 GATE -PRO(Generation And Transmission Expansion PROgram)모형을 이용하여 알아본 후, 이로 인하여 전기를 사용하는 용도에 따라 6가지 종별로 구분하는 현행 전기요금체계에 미치는 영향에 대하여 알아보고자 한다.

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Analysis of the LIGBT-based ESD Protection Circuit with Latch-up Immunity and High Robustness (래치-업 면역과 높은 감내 특성을 가지는 LIGBT 기반 ESD 보호회로에 대한 연구)

  • Kwak, Jae Chang
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.27 no.11
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    • pp.686-689
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    • 2014
  • Electrostatic discharge has been considered as a major reliability problem in the semiconductor industry. ESD reliability is an important issue for these products. Therefore, each I/O (Input/Output) PAD must be designed with a protection circuitry that creates a low impedance discharge path for ESD current. This paper presents a novel Lateral Insulated Gate Bipolar (LIGBT)-based ESD protection circuit with latch-up immunity and high robustness. The proposed circuit is fabricated by using 0.18 um BCD (bipolar-CMOS-DMOS) process. Also, TLP (transmission line pulse) I-V characteristic of proposed circuit is measured. In the result, the proposed ESD protection circuit has latch-up immunity and high robustness. These characteristics permit the proposed circuit to apply to power clamp circuit. Consequently, the proposed LIGBT-based ESD protection circuit with a latch-up immune characteristic can be applied to analog integrated circuits.

A Study on Linearity and Efficiency Enhancement of Power Amplifier (전력증폭기의 선형성 및 효율 향상에 관한 연구)

  • Jeon Joong-Sung
    • Journal of Advanced Marine Engineering and Technology
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    • v.29 no.6
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    • pp.618-627
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    • 2005
  • In this paper, we have compared and analyzed the performance of high amplifier using Doherty technique to improve linearity and efficiency of base station and repeater Power amplifier for WCDMA. This Doherty amplifier implements with 3dB branch line coupler and $90^{\circ}C$ transmission line The phase offset line is designed to maintain the high linearity and efficiency at the low efficiency Period of the power amplifier CW 1-tone experimental results at the WCDMA frequency $2.11{\sim}2.17GHz$ shows that Doherty amplifier which achieves power add efficiency(PAE) of 50% at 6dB back off the point from maximum output power 52.3 dBm, obtains higher efficiency of 13.3% than class AB Finding optimum bias Point after adjusted gate voltage, Doherty amplifier shows that $IMD_3$ improves 4dB.

Design of High-Speed VOQ Management Scheme for High Performance Cell/Packet Switch (고성능 셀/패킷 스위치를 위한 고속 VOQ 관리기 설계)

  • 정갑중;이범철
    • Proceedings of the IEEK Conference
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    • 2001.06b
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    • pp.369-372
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    • 2001
  • This paper presents the design of high-speed virtual output queue(VOQ) management scheme for high performance cell/packet switch, which has a serial cross bar structure. The proposed VOQ management scheme has been designed for wire-speed routing with a pipelined buffer management. It provides the tolerance of requests and grants data transmission latency between the VOQ manager and central arbiter using a new request control method that is based on a high-speed shifter. The designed VOQ manager has been implemented in a field programmable gate array chip with a 77MHz operating frequency, a 900-pin fine ball grid array package, and 16$\times$16 switch size.

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