• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.823-825
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• 2005

이동 기기의 저장장치로 널리 사용되고 있는 플래시 메모리는 하드웨어적 특성으로 인하여 쓰기 전 소거(erase before write) 기법이 사용되고 있다. 이러한 특성으로 인하여 플래시 메모리에서는 성능을 증진시키기 위한 기법이 필요하게 되었으며, 이러한 소프트웨어 모듈을 FTL이라 한다. 플래시 메모리의 용량이 크게 늘어나면서 디스크를 대체할 제품이 등장하고 있으며, 이러한 디스크가 일반 컴퓨터에서의 저장장치로 채택되는 경우가 많아지고 있다. 본 연구에서는 플래시 메모리 기반의 디스크를 이용한 윈도우 파일 시스템에서의 여러 FTL 알고리즘의 성능을 분석, 비교하고, FTL 알고리즘의 올바른 개선 방향을 제시한다.

• IEMEK Journal of Embedded Systems and Applications
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• v.16 no.5
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• pp.179-186
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• 2021

For stereo matching based on deep learning, the design of network structure is crucial to the calculation of matching cost, and the time-consuming problem of convolutional neural network in image processing also needs to be solved urgently. In this paper, a method of stereo matching using sparse loss volume in parallax dimension is proposed. A sparse 3D loss volume is constructed by using a wide step length translation of the right view feature map, which reduces the video memory and computing resources required by the 3D convolution module by several times. In order to improve the accuracy of the algorithm, the nonlinear up-sampling of the matching loss in the parallax dimension is carried out by using the method of multi-category output, and the training model is combined with two kinds of loss functions. Compared with the benchmark algorithm, the proposed algorithm not only improves the accuracy but also shortens the running time by about 30%.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.04a
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• pp.226-229
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• 2010

최근 프로세서가 코어 개수를 늘리는 구조로 발전함에 따라 병렬프로그래밍의 중요성이 더욱 강조되고 있다. 병렬프로그래밍에서 발생하는 공유자원에 대한 경쟁조건을 제어하기 위한 효율적인 방법으로 여러 가지 락-프리 동기화 기법이 제안되어 왔다. 그 중 소프트웨어 트랜잭션 메모리는 지금까지 하드웨어적인 방법과 소프트웨어적인 방법 등 여러 가지 방법으로 구현되었지만 여러 가지 하드웨어적인 제약과 기존의 소스코드를 수정해야 하는 문제점이 있다. 이러한 문제를 해결하기 위해 본 논문에서는 동적 코드 변환기술을 이용한 소프트웨어 트랜잭션 메모리 기법을 제안하고 기존 구현과 비교 평가하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.914-916
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• 2011

최근 낸드 플래시 메모리 기술의 발전으로 플래시 메모리의 용량이 증가함에 따라 다양한 장치에서 데이터 저장소로 사용되고 있으며, 하드디스크를 대체할 저장 매체로서 주목을 받고 있다. 하지만 낸드 플래시 메모리의 특성으로 인해 데이터를 삭제하더라도 일정 기간 삭제된 데이터가 메모리에 남아있게 되며, 이러한 특성으로 사용자의 중요 데이터가 보호되지 않은 상태로 저장되어 외부에 노출될 수 있다. 따라서 이런 특성을 보완하는 방법이 필요하며 본 논문에서는 낸드 플래시 메모리의 단점을 해결하기 위하여 낸드 플래시 메모리를 위한 시스템 소프트웨어인 FTL(Flash Translation Layer) 계층에서 암호화 알고리즘을 사용하여 데이터를 노출하지 않게 하는 방법을 제안한다.

• Clinical and Experimental Vaccine Research
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• v.13 no.2
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• pp.73-82
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• 2024

DNA cancer vaccines as an approach in tumor immunotherapy are still being investigated in preclinical and clinical settings. Nevertheless, only a small number of clinical studies have been published so far and are still active. The investigated vaccines show a relatively stable expression in in-vitro transfected cells and may be favorable for developing an immunologic memory in patients. Therefore, DNA vaccines could be suitable as a prophylactic or therapeutic approach against cancer. Due to the low efficiency of these vaccines, the administration technique plays an important role in the vaccine design and its efficacy. These DNA cancer vaccine delivery systems include physical, biological, and non-biological techniques. Although the pre-clinical studies show promising results in the application of the different delivery systems, further studies in clinical trials have not yet been successfully proven.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.25 no.4
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• pp.873-880
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• 2015

Since hardware-based kernel-integrity monitoring systems run in the environments that are isolated from the monitored OS, attackers in the monitored OS cannot undermine the security of monitoring systems. However, because the monitoring is performed by using physical addresses, the hardware-based monitoring systems are vulnerable to Address Translation Redirection Attack (ATRA) that manipulates virtual-to-physical memory translations. To ameliorate this problem, we propose a scheduler-based ATRA detection method. The method detects ATRA during the process scheduling by leveraging the fact that kernel scheduler engages every context switch of processes. We implemented a prototype on Android emulator and TizenTV, and verified that it successfully detected ATRA without incurring any significant performance loss.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.92-99
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• 2005

In this paper, we present a high-level design methodology applied on a network system-on-a-chip(SOC) using SystemC. The main target of our approach is to get optimum performance parameters for high network address translation(NAT) throughput. The Fast Ethernet media access controller(MAC) and its direct memory access(DMA) controller are modeled with SystemC in transaction level. They are calibrated through the cycle-based measurement of the operation of the real Verilog register transfer language(RTL). The NAT throughput of the model is within $\pm$10% error compared to the output of the real evaluation board. Simulation speed of the model is more than 100 times laster than the RTL. The validated models are used for intensive architecture exploration to find the performance bottleneck in the NAT router.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.5_6
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• pp.371-378
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• 2004

This paper presents the implementation and performance of the HVIA-GE card, which is a hardware implementation of the Virtual Interface Architecture (VIA) based on Gigabit Ethernet. The HVIA-GE card is a 32-bit/33MHz PCI adapter containing an FPGA for the VIA protocol engine and a Gigabit Ethernet chip set to construct a high performance physical network. HVIA-GE performs virtual-to-physical address translation, Doorbell, and send/receive completion operations in hardware without kernel intervention. In particular, the Address Translation Table (ATT) is stored on the local memory of the HVIA-GE card, and the VIA protocol engine efficiently controls the address translation process by directly accessing the ATT. As a result, the communication overhead during send/receive transactions is greatly reduced. Our experimental results show the maximum bandwidth of 93.7MB/s and the minimum latency of 11.9${\mu}\textrm{s}$. In terms of minimum latency HVIA-GE performs 4.8 times and 9.9 times faster than M-VIA and TCP/IP, respectively, over Gigabit Ethernet. In addition, the maximum bandwidth of HVIA-GE is 50.4% and 65% higher than M-VIA and TCP/IP respectively.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.12
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• pp.5375-5400
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• 2016

IOMMU is a hardware unit that is indispensable for DMA. Besides address translation and remapping, it also provides I/O virtual address space isolation among devices and memory access control on DMA transactions. However, currently commodity virtualization platforms lack of IOMMU virtualization, so that the virtual machines are vulnerable to DMA security threats. Previous works focus only on DMA security problem of directly assigned devices. Moreover, these solutions either introduce significant overhead or require modifications on the guest OS to optimize performance, and none can achieve high I/O efficiency and good compatibility with the guest OS simultaneously, which are both necessary for production environments. However, for simulated virtual devices the DMA security problem also exists, and previous works cannot solve this problem. The reason behind that is IOMMU circuits on the host do not work for this kind of devices as DMA operations of which are simulated by memory copy of CPU. Motivated by the above observations, we propose an IOMMU para-virtualization solution called PVIOMMU, which provides general functionalities especially DMA security guarantees for both directly assigned devices and simulated devices. The prototype of PVIOMMU is implemented in Qemu/KVM based on the virtio framework and can be dynamically loaded into guest kernel as a module, As a result, modifying and rebuilding guest kernel are not required. In addition, the device model of Qemu is revised to implement DMA access control by separating the device simulator from the address space of the guest virtual machine. Experimental evaluations on three kinds of network devices including Intel I210 (1Gbps), simulated E1000 (1Gbps) and IB ConnectX-3 (40Gbps) show that, PVIOMMU introduces little overhead on DMA transactions, and in general the network I/O performance is close to that in the native KVM implementation without IOMMU virtualization.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.12
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• pp.918-922
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• 2009

Naturally, block mapping FTL works well for sequential writes while page mapping FTL does well for random writes. To exploit their advantages, a practical FTL should be able to selectively apply a suitable scheme between page and block mappings for each write pattern. To meet that requirement, we propose a hybrid mapping FTL, which we call Janus-FTL, that distributes data to either block or page mapping areas. Also, we propose the fusion operation to relocate the data from block mapping area to page mapping area and the defusion operation to relocate the data from page mapping area to block mapping area. And experimental results of Janus-FTL show performance improvement of maximum 50% than other hybrid mapping FTLs.