• Journal of the Microelectronics and Packaging Society
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• v.30 no.3
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• pp.88-93
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• 2023

As the demand for High Bandwidth Memory (HBM) increases and the handling capability of larger wafers expands, ensuring reliable Total Thickness Variation (TTV) measurement for stacked wafers becomes essential. This study presents the design of a measurement module capable of measuring TTV across the entire area of a 300mm wafer, along with estimating potential mechanical measurement errors. The module enables full-area measurement by utilizing a center chuck and lift pin for wafer support. Modal analysis verifies the structural stability of the module, confirming that both the driving and measuring parts were designed with stiffness exceeding 100 Hz. The mechanical measurement error of the designed module was estimated, resulting in a predicted measurement error of 1.34 nm when measuring the thickness of a bonding wafer with a thickness of 1,500 ㎛.

• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.8-13
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• 2023

High bandwidth memory a core technology of the future memory semiconductor industry, is attracting attention. Temporary bonding and debonding process technology, which plays an important role in high bandwidth memory process technology, is also being studied. In this process, total thickness variation is a major factor determining wafer performance. In this study, the reliability of the equipment measuring total thickness variation is identified, and the servo motor settling, and wafer total thickness variation measurement accuracy are analyzed. As for the experimental variables, vacuum, acceleration time, and speed are changed to find the most efficient value by comparing the stabilization time. The smaller the vacuum and the larger the radius, the longer the settling time. If the radius is small, high-speed rotation performance is good, and if the radius is large, low-speed rotation performance is good. In the future, we plan to conduct an experiment to measure the entire of the wafer.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.1-5
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• 2005

The grinding process is replacing lapping and etching process because significant cost savings and performance improvemnets is possible. This paper presents the experimental results of wafer grinding. A three-variable two-level full factorial design was employed to reveal the main effects as well as the interaction effects of three process parameters such as wheel rotational speed, chuck table rotational speed and feed rate on TTV and STIR of wafers. The chuck table rotaional speed was a significant factor and the interaction effects was significant. The ground wafer shape was affected by surface shape of chuck table.

• Tribology and Lubricants
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• v.32 no.2
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• pp.61-66
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• 2016

Total thickness variation (TTV), BOW, and surface roughness are essential characteristics for high quality sapphire substrates. Many researchers have attempted to increase removal rate by controlling the key process parameters like pressure and velocity owing to the high cost of consumables in sapphire chemical mechanical polishing (CMP). In case of the pressure approach, increased pressure owing to higher deviation of pressure over the wafer leads to significant degradation of the TTV. In this study, the authors focused on reducing TTV under the high-pressure conditions. When the production equipment polishes multiple wafers attached on a carrier, higher loads seem to be concentrated around the leading edge of the head; this occurs because of frictional force generated by the combination of table rotation and the height of the gimbal of the polishing head. We believe the skewed pressure distribution during polishing to be the main reason of within-wafer non-uniformity (WIWNU). The insertion of a hub ring between the polishing head and substrate carrier helped reduce the pressure deviation. Adjusting the location of the hub ring enables tuning of the pressure distribution. The results indicated that the position of the hub ring strongly affected the removal profile, which confirmed that the position of the hub ring changes the pressure distribution. Furthermore, we analyzed the deformation of the head via finite element method (FEM) to verify the pressure non-uniformity over the contact area Based on experiment and FEM results, we determined the optimal position of hub ring for achieving uniform polishing of the substrate.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.25 no.1
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• pp.13-19
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• 2015

Among the various possible factors affecting the Minority Carrier Life Time (MCLT) of the mc-Si crystal, dislocations formed during the cooling period after solidification were found to be a major element. It was confirmed that other defects such as grain boundary or twin boundary were not determinative defects affecting the MCLT because most of these defects seemed to be formed during the solidification period. With a measurement of total thickness variation (TTV) and bow of the silicon wafers, it was found that residual stress remaining in the mc-Si crystal might be another major factor affecting the MCLT. Thus, it is expected that better quality of mc-Si can be grown when the cooling process right after solidification is carried out as slow as possible.

• Design & Manufacturing
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• v.18 no.2
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• pp.9-16
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• 2024

Recently, there has been extensive research conducted on the miniaturization of semiconductors and the improvement of their integration to achieve high-quality and high-performance electronic devices. To integrate and miniaturize multiple semiconductors, thin and precise wafers are essential. The backgrinding process, which involves high-precision processing, is necessary to achieve this. The backgrinding system is used to grind and polish the back side of the wafer to reduce its thickness to ㎛ units. This enables the high integration and miniaturization of semiconductors and a flattening process to allow for detailed circuit design, ultimately leading to the production of IC chips. As the backgrinding system performs precision processing at the ㎛ unit, it is crucial to determine the stability of the equipment's rigidity. Additionally, the flatness and surface roughness of the processed wafer must be checked to confirm the processability of the backgrinding system. IIn this paper, the goal is to verify the processability of the back grinding system by analyzing the natural frequency and resonance frequency of the equipment through computer simulation and measuring and analyzing the flatness and surface roughness of wafers processed with backgrinding system. It was confirmed whether processing damage occurred due to vibration during the backgrinding process.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.104-107
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• 2005

Recently, according to the development of semiconductor industry, needed to high-integration and high-functionality. These changes are required for silicon wafer of large scale diameter and precision of TTV (Total Thickness variation). So, in this research, suggest that the method of monitoring system is using motor current. This method is needed for observation of silicon wafer grinding process. Motor current sensor is consisted of hall sensor. Hall sensor is known to catching of change of current. Received original signal is converted to the diginal, then, it is calculated RMS values, and then, it is analysed in computer. Generally, the change of force is relative to the change of current, So this reason, in this research tried to monitoring of motor current change, and then, it will be applied to analysis for silicon wafer grinding process. using motor current sensor.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.24 no.5
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• pp.190-195
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• 2014

Because of the temperature gradient occurring during the growth of the ingot with directional solidification method, defects are generated and the residual stress is produced in the ingot. Changing the growth and cooling rate during the crystal growth process will be helpful for us to understand the defects and residual stress generation. The defects and residual stress can affect the properties of wafer. Generally, it was found that the size of grains and twin boundaries are smaller at the top area than at the bottom of the ingot regardless of growth and cooling condition. In addition to that, in the top area of silicon ingot, higher density of dislocation is observed to be present than in the bottom area of the silicon ingot. This observation implies that higher stress is imposed to the top area due to the faster cooling of silicon ingot after solidification process. In the ingot with slower growth rate, dislocation density was reduced and the TTV (Total Thickness Variation), saw mark, warp, and bow of wafer became lower. Therefore, optimum growth condition will help us to obtain high quality silicon ingot with low defect density and low residual stress.