• Journal of computational fluids engineering
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• v.12 no.4
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• pp.68-73
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• 2007

Computational Fluid Dynamics (CFD) approach is now playing an important role in the engineering process in these days. Generating proper grid system in time for the region of interest is prerequisite for the efficient numerical calculation of flow physics using CFD approach. Grid generation is, however, usually considered as a major obstacle for a routine and successful application of numerical approaches in the engineering process. CFD approach based on the unstructured grid system is gaining popularity due to its simplicity and efficiency for generating grid system compared to the structured grid approaches, especially for complex geometries. In this paper an automated triangular surface grid generation using CAD(Computer Aided Design) surface data is proposed. According to the present method, the CAD surface data imported in the STL(Stereo-lithography) format is processed to identify feature edges defining the topology and geometry of the surface shape first. When the feature edges are identified, node points along the edges are distributed. The initial fronts which connect those feature edge nodes are constructed and then they are advanced along the CAD surface data inward until the surface is fully covered by triangular surface grid cells using Advancing Front Method. It is found that this approach can be implemented in an automated way successfully saving man-hours and reducing human-errors in generating triangular surface grid system.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.8
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• pp.2764-2782
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• 2021

Existing city-level boundary nodes identification methods need to locate all IP addresses on the path to differentiate which IP is the boundary node. However, these methods are susceptible to time-delay, the accuracy of location information and other factors, and the resource consumption of locating all IPes is tremendous. To improve the recognition rate and reduce the locating cost, this paper proposes an algorithm for city-level boundary node identification based on bidirectional approaching. Different from the existing methods based on time-delay information and location results, the proposed algorithm uses topological analysis to construct a set of candidate boundary nodes and then identifies the boundary nodes. The proposed algorithm can identify the boundary of the target city network without high-precision location information and dramatically reduces resource consumption compared with the traditional algorithm. Meanwhile, it can label some errors in the existing IP address database. Based on 45,182,326 measurement results from Zhengzhou, Chengdu and Hangzhou in China and New York, Los Angeles and Dallas in the United States, the experimental results show that: The algorithm can accurately identify the city boundary nodes using only 20.33% location resources, and more than 80.29% of the boundary nodes can be mined with a precision of more than 70.73%.

• International Journal of Naval Architecture and Ocean Engineering
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• v.12 no.1
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• pp.832-842
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• 2020

The coordination control of multiple Underactuated Underwater Vehicles (UUVs) moving in three dimensional space is investigated in this paper. The coordinated path following control task is decomposed into two sub tasks, that is, path following control and coordination control. In the spatial curve path following control task, path following error dynamics is build in the Serret-Frenet coordinate frame. The virtual reference object can be chosen freely on the desired spatial path. Considering the speed of the UUV, the line-of-sight navigation is introduced to help the path following errors quickly converge to zero. In the coordination control sub task, the communication topology of multiple UUVs is described by the graph theory. The speed of each UUV is adjusted to achieve the coordination. The path following system and the coordination control system are viewed as the feedback connection system. Input-to-state stable of the coordinated path following system can be proved by small gain theorem. The simulation experiments can further demonstrate the good performance of the control method.

• Proceedings of the KSR Conference
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• 2009.05a
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• pp.396-405
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• 2009

An interlocking equipment of railway signalling systems should have very high functional safety and reliability properties because of its vital railway protection functionality. In order to achieve the required safety and reliability level, an engineer, in general, designs and implements the interlocking equipment to operate under RTOS(Realtime Operating System) environment, and the control hardware architecture redundant to cope with the random failures of system or subsystem. In such an architecture, it's very difficult to implement the interlocking equipment to communicate with various interface systems including the signal operator's terminal. In this paper, we propose a dual ethernet network topology and dual packet seamless transfer protocol algorithm for railway signaling system such as the interlocking equipment. We verify in this paper that the proposed DPST protocol algorithm has the evidence of its robust properties against the random hardware faults and communication errors. The proposed communication structure and algorithm is implemented in the electronic interlocking equipment for the private railway system of Hyundai Steel Company and its performance and properties are validated on the guideline of European Railway Standard EN50159.

• Journal of KIISE:Software and Applications
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• v.34 no.11
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• pp.1001-1010
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• 2007

HMM tends to output high probability for not only the proper class data but confusable class data, since the modeling power increases as the number of parameters increases. Thus it may not be helpful for discrimination to simply increase the number of parameters of HMM. We proposed two methods in this paper. One is a CMC(Confusion Likelihood Model Selection Criterion) using confusion class data probability, the other is a new recognition method, RCM(Recognition Using Confusion Models). In the proposed recognition method, confusion models are constructed using confusable class data, then confusion models are used to depress misrecognition by confusion likelihood is subtracted from the corresponding standard model probability. We found that CMC showed better results using fewer number of parameters compared with ML, ALC2, and BIC. RCM recorded 93.08% recognition rate, which is 1.5% higher result by reducing 17.4% of errors than using standard model only.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.4
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• pp.364-375
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• 2014

Parametric array transducers are used for long-range and highly directional communication in an underwater environments. The power amplifiers for parametric array transducers should have sufficient linear output characteristic and high efficiency to avoid communication errors, system heating, and fuel problems. But the conventional power amplifier with fixed source voltage is very low efficient due to large power loss by the big difference between the fixed source voltage and the amplifier output voltage. Thus to solve the problems this paper proposes the high efficiency power amplifier for parametric array transducers. The proposed power amplifier ensures high linearity of output characteristic by utilizing the push-pull class B type amplifier and furthermore gets high efficiency by applying the envelope tracking technique that variable source voltage tracks the envelope of the amplified signal. Also the paper suggests the detailed circuit topology and design guideline of class B push-pull type amplifier and variable output voltage AC/DC converter. Its characteristics are verified by the detailed simulation and experimental results.

• Nuclear Engineering and Technology
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• v.54 no.7
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• pp.2444-2452
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• 2022

The field-programmable gate array (FPGA) is gaining popularity in industrial automation such as nuclear power plant instrumentation and control (I&C) systems due to the benefits of having non-existence of operating system, minimum software errors, and minimum common reason failures. Separate functions can be processed individually and in parallel on the same integrated circuit using FPGAs in comparison to the conventional microprocessor-based systems used in any plant operations. The use of FPGAs offers the potential to minimize complexity and the accompanying difficulty of securing regulatory approval, as well as provide superior protection against obsolescence. Wireless sensor networks (WSNs) are a new technology for acquiring and processing plant data wirelessly in which sensor nodes are configured for real-time signal processing, data acquisition, and monitoring. ZigBee (IEEE 802.15.4) is an open worldwide standard for minimum power, low-cost machine-to-machine (M2M), and internet of things (IoT) enabled wireless network communication. It is always a challenge to follow the specific topology when different Zigbee nodes are placed in a large network such as a plant. The research article focuses on the hardware chip design of different topological structures supported by ZigBee that can be used for monitoring and controlling the different operations of the plant and evaluates the performance in Vitex-5 FPGA hardware. The research work presents a strategy for configuring FPGA with ZigBee sensor nodes when communicating in a large area such as an industrial plant for real-time monitoring.

• Journal of the Korean Institute of Intelligent Systems
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• v.25 no.3
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• pp.279-286
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• 2015

The rapid increase of the current marine accidents is mainly due to the human execution errors. In an effort to address this, various kinds of researches such as construction of the digital vessels and vessel information monitoring systems have been conducted. But for safe navigation of vessels, it lack on systems study which can efficiently store, utilize and manage the mass data accepted by the vessel. In this paper, we propose a VWS(Virtual World System) that is based on the architecture of intelligent systems RVC(Reactive Layer-Virtual World-Considerative Layer) model of intelligent autonomous navigation system. VWS is responsible to store all the necessary information for safe navigation of the vessel and the information services to the sub-system of intelligent autonomous navigation system. VWS uses topology database to express the specific problem area, and utilizes a scheduling to reflect the characteristics of the real-time processing environment. Also, Virtual World defines API for the system to reflect the characteristics of the distributed processing environment. As a case study, the VWS is applied to a intelligent ship autonomous navigation system, and simulation is done to prove the effectiveness of the proposed system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.673-684
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• 2003

A degenerated differential pair has been widely used as a standard topology for digitally programmable CMOS VGAs. A variable degeneration resistor has been implemented using a resistor string or R-2R ladder with MOSFET switches. However, in the VGAs using these conventional methods, low-voltage and high-speed operation is very hard to achieve due to the dc voltage drop over the degeneration resistor. To overcome this problem a new variable degeneration resistor is proposed where the dc voltage drop is almost removed. Using the proposed gain control scheme, a low-voltage and high-speed CMOS VGA is designed. HSPICE simulation results using a 0.25${\mu}{\textrm}{m}$ CMOS process parameters show that the designed VGA provides a 3dB bandwidth of 360MHz and a 80dB gain control range in 2dB step. Gain errors are less than 0.4dB at 200MHz and less than l.4dB at 300MHz. The designed circuit consumes 10.8mA from a 2.5V supply and its die area is 1190${\mu}{\textrm}{m}$${\times}$360${\mu}{\textrm}{m}$.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.43-55
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• 2003

A degenerated differential pair has been widely used as a standard topology for digitally programmable CMOS VGAs. A variable degeneration resistor has been implemented using a resistor string or R-2R ladder with MOSFET switches. However, in the VGAs using these conventional methods, low-voltage and high-speed operation is very hard to achieve due to the dc voltage drop over the degeneration resistor. To overcome the problem a new variable degeneration resistor is proposed where the dc voltage drop is almost removed. The proposed gain control scheme makes it easy to implement a low-voltage and high-speed VGA. This paper describes the problems existed in conventional methods, the principle and advantages of the proposed scheme, and their performance comparison in detail. A CMOS VGA cell is designed using the proposed degeneration resistor. The 3dB bandwidths are greater than 650㎒ and the gain errors are less than 0.3dB in a gain control range from -12dB to +12dB in 6dB steps. It consumes 3.1㎃ from a 2.5V supply voltage.