• E2M - 전기 전자와 첨단 소재
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• 제7권2호
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• pp.145-151
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• 1994

The multi-dielectric layer SiOz/Si3N4/SiO2(ONO) is used to scale down the memory device. In this paper, the change of composition in ONO layer due to the process condition and the conduction mechanism are observed. The composition of the oxide film grown through the oxidation of nitride film is analyzed using auger electron spectroscopy(AES). AES results show that oxygen concentration increases at the interface between oxide and nitride layers as the thickness -of the top oxide layer increases. Results of I-V measurement show that the insulating properties improve as the thickness of the top oxide layer increases. But when the thickness of the nitride layer decreases below 63.angs, insulating peoperties of film 28.angs. of top oxide and film 35.angs. turn over showing that insulating property of film 28.angs. of top oxide is better than that of film 35.angs. of top oxide. This phenomenon of turn over is thought as the result of generation of surface state due to oxygen flow into nitride during oxidation process. As the thickness of the top oxide and nitride increases, the electrical breakdown field increases, but when the thickness of top oxide reaches 35.angs, the same phenomenon of turn over occurs. Optimum film thickness for scaled multi-layer dielectric of memory device SONOS is estimated to be 63.angs. of nitride layer and 28.angs. of top oxide layer. In this case, maximum electrical breakdown field and leakage current are 18.5[MV/cm] and $8{\times}{10^-12}$[A], respectively.

• Nuclear Engineering and Technology
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• 제51권4호
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• pp.996-1007
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• 2019

We investigated the influence of the aspect ratio (H/R) of the oxide layer on the reactor vessel heating in three-layer configuration. Based on the analogy between heat and mass transfers, we performed mass transfer experiments to achieve high Rayleigh numbers ranging from $6.70{\times}10^{10}$ to $7.84{\times}10^{12}$. Two-dimensional (2-D) semi-circular apparatuses having the internal heat source were used whose surfaces of top, bottom and side simulate the interfaces of the oxide layer with the light metal layer, the heavy metal layer, and the reactor vessel, respectively. Multi-cell flow pattern was identified when the H/R was reduced to 0.47 or less, which promoted the downward heat transfer from the oxide layer and possibly mitigated the focusing effect at the upper metallic layer. The top boundary condition greatly affected the natural convection of the oxide layer due to the presence of secondary flows underneath the cold light metal layer.

• 전자공학회논문지A
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• 제32A권9호
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• pp.121-127
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• 1995

We have analyzed the double insulating layer consisting of anodic oxide and ZnS through TEM experiments. The use of double insulating layer for HgCdTe surface passivation is one of the promising passivation method which has been recently studied deeply and the double insulating layer is formed by the evaporation of ZnS on the top of anodic oxide layer grown in H$_{2}$O$_{2}$ electrolyte. The structure of anodic oxide layer on HgCdTe is amorphous but the structure of oxide layer after the evaporation of ZnS has been changed to micro-crystalline. The interface layer of 150.angs. thickness has been found between ZnS and anodic oxide layer and is estimated to be ZnO layer. The results of analysis on the chemical components of ZnS, the interface layer and anodic oxide layer have showed that Zn has diffused into the anodic oxide layer deeply while Hg has been significantly decreased from HgCdTe bulk to the top of oxide layer. The formation of ZnO interface layer and the change of structure of anodic oxide layer after the evaporation of ZnS are estimated to be defects or to induce the defects which might possibly affect the increase of the positive fixed charges shown in C-V measurements of HgCdTe MIS.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
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• pp.1081-1081
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• 2002

Top emission organic EL devices were fabricated by using metal-doped cathode interface layer to achieve low drive voltages. Also, facing-targets-type sputtering was used to sputter indium-tin oxide layer on top of organic active layer. The devices fabricated in this study showed reasonably high external quantum efficiency of about 1 % which is comparable to that of bottom-emission-type devices.

• E2M - 전기 전자와 첨단 소재
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• 제7권3호
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• pp.231-235
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• 1994

The multi-dielectric layer $SiO_2$/$Si_3{N_4}$/$SiO_2$ (ONO) is used to improve charge retention and to scale down the memory device. The nitride layer of MNOS device is oxidize to form ONO system. During the oxidation of the nitride layer, the change of thickness of nitride layer and generation of interface state between nitride layer and top oxide layer occur. In this paper, effects of oxidation of the nitride layer is studied. The decreases of the nitride layer due to oxidation and trapping characteristics of interface state of multi layer dielectric film are investigated through the C-V measurement and F-N tunneling injection experiment using SONOS capacitor structure. Based on the experimental results, carrier trapping model for maximum flatband voltage shift of multi layer dielectric film is proposed and compared with experimental data. As a results of curve fitting, interface trap density between the top oxide and layer is determined as being $5{\times}10^11$~$2{\times}10^12$[$eV^1$$cm^2$].

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.212-212
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• 2013

We fabricate and characterize top gate Graphene transistor using aluminum oxide as a gate insulator by atomic layer deposition (ALD). It is found that due to absence of functional group and dangling bonds, ALD of metal oxide is difficult on Graphene. Here we used 4-mercaptopheneol as a functionalization layer on Graphene to facilitate uniform oxide coverage. Contact angle measurement and Atomic force microscopy were used to confirm uniform oxide coverage on Graphene. Raman spectroscopy revealed that functionalization with 4-mercaptopheneol does not induce any defect peak on Graphene. Our device shows mobility values of 4,000 $cm^2/Vs$ at room temperature which also suggest top gate stack does not significantly increase scattering. The noncovalent functionalization method is non-destructive and can be used to grow ultra-thin dielectric for future Graphene applications.

• 전자공학회논문지D
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• 제36D권10호
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• pp.17-22
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• 1999

이 논문에서는 플래시 EEPROM 셀에서의 데이터 보존 특성을 개선하기 위해서 IPD(inter-poly-dielectrics) 층을 사용하는 새로운 제안에 관한 연구 결과들을 논의하였다. 이 연구를 위하여 약 10nm 두께의 게이트 산호막을 갖으며 또한 ONO 또는 ONON IPD 층을 갖는 적층형-게이트 플래시 EEPROM 셀들을 제작하였다. 측정 결과를 보면 ONO IPD 층을 갖는 소자들은 데이터 보존 특성이 심각하게 열화 되었으며, 그 특성의 활성화 에너지도 0.78 eV로 플래시 EEPROM 셀을 위하여 요구되는 최소 값(1.0 eV)보다 상당히 낮았다. 이는 구동 소자용 트랜지스터(peripheral MOSFET) 소자들의 게이트 산호막을 형성하기 위한 건열산화 공정 바로 직전에 실시하는 세정 공정 동안 IPD 층의 상층 산화막의 일부 또는 전부가 식각되었기 때문인 것으로 믿어진다. 반면에, ONON IPD 층을 갖는 소자들의 데이터 보존 특성은 상단히 (약 50% 이상) 개선되었으며 활성화 에너지도 1.1 eV인 것으로 나타났다. 이는 IPD 층에서 상층 산화막위에 있는 질화막이 그 세정 공정 동안 산화막이 식각되는 것을 방지해 주기 때문임에 틀림없다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
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• pp.714-716
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• 2002

Indium tin oxide (ITO) was used as the top anode of top emission inverted organic light emitting diodes (TEIOLEDs). TEIOLEDs were fabricated by deposition of an aluminum bottom cathode, an N,N'-diphenyl-N,N'-bis(3-methylphenyl)-1, 1'-diphenyl-4, 4 1'-diamine (TPD) hole transport layer, a tris-8-hydroxyquinoline aluminum ($Alq_3$) emission layer, and an ITO top anode sequentially. ITO was deposited by r.f. magnetron sputtering without $O_2$ flow during the deposition. After the deposition, the deposited ITO layer was kept under oxygen atmosphere for the oxidation. The characteristics of the TEOILED were affected significantly by the post-deposition oxidation condition.

• 전자공학회논문지D
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• 제36D권10호
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• pp.9-16
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• 1999

Flash EEPROM 셀에서 기존의 ONO 구조의 IPD를 사용하면 peripheral MOSFET의 게이트 산화막을 성장할 때에 사용되는 세정 공정을 인하여 ONO 막의 상층 산화막이 식각되어 전하 보존 특성이 크게 열화되었으나 IPD 공정에 ONON 막을 사용하면 그 세정 공정시에 상층 질화막이 상층 산호막이 식각되는 것을 방지시켜 줌으로 전하보존 특성이 크게 개선되었다. ONON IPD 막을 갖고 있는 Flash EEPROM 셀의 전화 보존 특성의 모델링을 위하여 여기서는 굽는(bake) 동안의 전하 손실로 인한 문턱전압 감소의 실험식으로 ${\Delta}V_t\; = \;{\beta}t^me^{-ea/kT}$을 사용하였으며, 측정 결과 ${\beta}$=184.7, m=0.224, Ea=0.31 eV의 값을 얻었다. 이러한 0.31 eV의 활성화 에너지 값은 굽기로 인한 문턱전압의 감소가 층간 질화막 내에서의 트립된 전자들의 이동에 의한 것임을 암시하고 있다. 한편, 그 모델을 사용한 전사 모사의 결과는 굽기의 thermal budget이 낮은 경우에 실험치와 잘 일치하였으나, 반면에 높은 경우에는 측정치가 전사 모사의 결과보다 훨씬 더 크게 나타났다. 이는 thermal budge가 높은 경우에는 프로그램시에 층간 질화막 내에 트립되어 누설전류의 흐름을 차단해 주었던 전자들이 빠져나감으로 인하여 터널링에 의한 누설전류가 발생하였기 때문으로 보여졌다. 이러한 누설전류의 발생을 차단하기 위해서는 ONON 막 중에서 층간 질화막의 두께는 가능한 얇게 하고 상층 산화막의 두께는 가능한 두껍게 하는 것이 요구된다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.354-355
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• 2009

In the fabrication of inverted top-emitting organic light emitting diodes (ITOLEDs), the sputtering process is needed for deposition of transparent conducting oxide (TCO) as top anode. Energetic particle bombardment, however, changes the physical properties of underlying layers. In this study, we examined plasma process effects on tungsten oxide ($WO_3$) hole injection layer (HIL). From our results, we suggest the theoretical mechanism to explain the correlation between the physical property changes caused by plasma process on $WO_3$ HIL and degradation of device performances.