• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.7
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• pp.28-38
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• 1997

Previously, we have proposed the M-BECM(Modified-Band Edge Component Maximization), which is a symbol synchronization algorithm based on spectral line method for all-digital high speed digital communications. However, Until now, the characteristics of the timing detector based on the spectral line method including M-BECM was not analyzed, particularly the effect of a timing offset at the optimal convergence pont. In this paper, we analyze the timing dtector's characteristics of the M-BECM and present optimal design value. First, the expression for the timing detector's mean value(often called its S-Curver) as a function of the normalized symbol timing offset is derived. Next, the P $D_{bias}$, the value for compensating the timing offset at an optimal convergence point, and the bandwidth of bandpass filter in the timing detector are calculated. It is also shown and analyzed that the P $D_{bias}$ is affected by varuous factors such as the excess bandwidth of input signal, frequency offsets, noise and particularly, the excess bandwidth of input signal is a major parameter to decide P $D_{bias}$. Finally, analytic resutls are compared to simulation results.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.1
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• pp.1-10
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• 2001

In this paper, a multistage parallel interference canceller (MPIC) and a partial multistage parallel interference canceller (PMPIC) are employed as a technique for improving the performance of the asynchronous DS-CDMA systems. The degree of the effect of the timing errors and phase errors on the interference cancellation capability of two types of cancellers is theoretically analyzed and the computer simulation is performed to confirm the analytical results. From the results, the large performance improvement is obtained by employing MPIC and PMPIC with perfect synchronization over the conventional matched filter, and the performance improvement obtained by MPIC and PMPIC is very close to each other as the number of the stage of MPIC and PMPIC increases. When the timing errors and phase errors are considered (in the case of imperfect synchronization), the performance improvement reduces as the performance degradation at the first stage (no cancellation) has a bad effect on the decision statistics at each stage. However MPIC and PMPIC have the strong interference cancellation capability in spite of imperfect synchronization as the number of the stage increases. An interference canceller, which has the strong interference cancellation capability as well as lower complexity for the implementation, is needed for practical systems with timing errors and phase errors because the perfect synchronization is impossible. Therefore, the excellent tradeoff between complexity and performance offered by PMPIC makes it an attractive approach for practical systems.

• Journal of the Institute of Convergence Signal Processing
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• v.15 no.4
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• pp.169-175
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• 2014

NG-SDH system is connected with networks throughout optical fibers. Network synchronization controller is a necessary for the data synchronization in each optical transmission system. In this paper, we have design and implementation the network synchronization controller using SOPC(system on a programmable chip) design technic. For this network synchronization controller we use FPGA in Altera. FPGA includes 32bit CPU, DPRAM(dual port ram), digital input/output port, transmitter and receiver framer, phase difference detector. We also confirm that designed network synchronization controller satisfies the ITU-T G.813 timing requirements.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.53-54
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• 2007

As Cable Network is developing for 2-way high speed data service, it should be developed to transfer high speed data using limited bandwidth. If QAM is using for this, synchronization algorithms become important system parameters. In this paper, we present two methods of coarse timing recovery using CAZAC sequence for cable modem uplink.

• Journal of Advanced Navigation Technology
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• v.18 no.5
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• pp.429-436
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• 2014

This paper proposes three methods of the time synchronization for Pseudolite and GPS and analyzes pseudolite time synchronization error factors for software based performance evaluation on proposed time synchronization methods. Proposed three time synchronization methods are pseudolite time synchronization station construction method, method by using UTC(KRIS) clock source and GPS timing receiver based time synchronization method. Also, we analyze pseudolite time synchronization error factors such as errors of pseudolite clock and reference clock, time delay as clock transmission line, measurement error of time interval counter and error as clock synchronization algorithm to design simulation platform for performance evaluation of pseudolite time synchronization.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.10
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• pp.1264-1274
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• 1999

본 논문에서는 분산된 클록들을 주기적으로 동기화 시키는 분산 실시간 시스템에서 시간적 제약을 만족시키기 위한 정적/동적 시간 제약(timing constraint) 변환 기법을 제안한다. 전형적인 이산클록동기화(discrete clock synchronization) 알고리즘은 클록의 값을 순간적으로 조정하여 클록의 시간이 불연속적으로 진행한다. 이러한 시간상의 불연속성은 시간적 이벤트를 잃어버리거나 다시 발생시키는 오류를 범하게 한다.클록 시간의 불연속성을 피하기 위해 일반적으로 연속클록동기화(continuous clock synchronization) 기법이 제안되고 있지만 소프트웨어적으로 구현되면 많은 오버헤드를 유발시키는 문제점이 있다. 본 논문에서는 시간적 제약을 동적으로 변환시키는 DCT (Dynamic Constraint Transformation) 기법을 제안하였으며, 이를 통해 기존의 이산클록동기화 알고리즘을 수정하지 않고서도 클록 시간의 불연속성에 의한 문제점들을 해결할 수 있도록 하였다. 아울러 DCT에 의해 이산클록동기화 하에서 생성된 태스크 스케쥴이 연속클록동기화에 의해 생성된 스케쥴과 동일함을 증명하여 DCT의 동작이 이론적으로 정확함을 증명하였다.또한 분산 실시간 시스템에서 지역 클록(local clock)이 기준 클록과 완벽하게 일치하지 않아서 발생하는 스케쥴링상의 문제점을 다루었다. 이를 위해 먼저 두 가지의 스케쥴링 가능성, 지역적 스케쥴링 가능성(local schedulability)과 전역적 스케쥴링 가능성(global schedulability)을 정의하고, 이를 위해 시간적 제약을 정적으로 변환시키는 SCT (Static Constraint Transformation) 기법을 제안하였다. SCT를 통해 지역적으로 스케쥴링 가능한 태스크는 전역적으로 스케쥴링이 가능하므로, 단지 지역적 스케쥴링 가능성만을 검사하면 스케쥴링 문제를 해결할 수 있도록 하였고 이를 수학적으로 증명하였다.Abstract In this paper, we present static and dynamic constraint transformation techniques for ensuring timing requirements in a distributed real-time system possessing periodically synchronized distributed local clocks. Traditional discrete clock synchronization algorithms that adjust local clocks instantaneously yield time discontinuities. Such time discontinuities lead to the loss or the gain of events, thus raising serious run-time faults.While continuous clock synchronization is generally suggested to avoid the time discontinuity problem, it incurs too much run-time overhead to be implemented in software. We propose a dynamic constraint transformation (DCT) technique which can solve the problem without modifying discrete clock synchronization algorithms. We formally prove the correctness of the DCT by showing that the DCT with discrete clock synchronization generates the same task schedule as the continuous clock synchronization.We also investigate schedulability problems that arise when imperfect local clocks are used in distributed real-time systems. We first define two notions of schedulability, global schedulability and local schedulability, and then present a static constraint transformation (SCT) technique. The SCT ensures that it is sufficient to check the schedulability of a task locally in a node with a local clock, since the global schedulability of the task is derived from its local schedulability through SCT. We formally prove the correctness of SCT.

• Journal of Positioning, Navigation, and Timing
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• v.9 no.4
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• pp.397-403
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• 2020

In order to synchronize a remote system time to the reference time like Coordinated Universal Time (UTC), it is required to compare the time difference between the two clocks. The time comparison data may have some outliers and the time synchronization performance can be significantly degraded if the outliers are not removed. Therefore, it is required to employ an effective outlier detection algorithm for keeping high accurate system time. In this paper, an outlier detection method is presented for the time difference data of GNSS time transfer receivers. The time difference data between the system time and the GNSS usually have slopes because the remote system clock is under free running until synchronized to the reference clock time. For investigating the outlier detection performance of the proposed algorithm, simulations are performed by using the time difference data of a GNSS time transfer receiver corrected to a free running Cesium clock with intentionally inserted outliers. From the simulation, it is investigated that the proposed algorithm can effectively detect the inserted outliers while conventional methods such as modified Z-score and adjusted boxplot cannot. Furthermore, it is also observed that the synchronization performance can be degraded to more than 15% with 20 outliers compared to that of original data without outliers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.2
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• pp.141-154
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• 2013

The technology of precise time-synchronization between signal receive devices for separation distance operation can be a key point for the technology with TDoA-based system. We propose a new method for the higher accuracy of system's time-synchronization in this paper, which uses OCXO and DPLL with high accuracy to achieve phase synchronization at 1 pps (pulse per second) of signal. And the method receive time value from a GPS satellite. Essentially, the performance of GPS with high accuracy refers to long-term frequency stability for its reliability. As per the characteristic, as the GPS timing signals are synchronized continuously, the accuracy of time-synchronization gets improved proportionally. Therefore, if the time synchronization is accomplished, the accuracy of the synchronization can be up to 0.001 ppb (part per billion). Through the improved accuracy of the time-synchronization, the measurement error of TDOA-based location detection technology is evaluated. Consequently, we verify that TDoA-based location measurement error can be greatly improved via using the improved method for time-synchronization error.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.6A
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• pp.575-585
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• 2006

In Orthogonal Frequency Division Multiple Access (OFDMA) systems, timing synchronization in uplink is accomplished by an initial uplink synchronization called an initial ranging process. The Base Station's receiver synchronizes the symbol timing to specific user's symbol and the other user's symbols have some Symbol Timing Offset (STO). Linear phase shift is occurred by each user's STO in an OFDMA symbol. The Multiple Access Interference (MAI) caused by the summation of each user's linear phase shift degrades the performance of ranging code detection. In this paper, we propose an initial ranging symbol structure with common ranging code for phase shift estimation and compensation. We car estimate the average of phase shift that is generated by each user's STO and compensate this phase shift by using common ranging code. This scheme will suppress the MAI and provide better detection performance than conventional process.

• Proceedings of the Optical Society of Korea Conference
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• 2000.02a
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• pp.276.2-278
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• 2000

In a recent years, a number of approaches have been studied, including passive, active, and hybrid mode-locking of semi-conductor lasers for short pulse generation and research has been devoted to achieve low timing-jitter operation since the timing jitter is unfavorable for system applications. Among the methods of mode locking, passive mode locking does not need external rf drives, and therefore the operation and fabrication procedures are simplified. In spite of these attractive advantages of passive mode-locked laser, it has critical drawbacks such as large timing jitter and the difficulty in synchronization with external circuits. Their inherent large timing jitter value was shown to be suppressed to certain levels by means of hybrid mode-locking technique$^{(1)}$ , where the saturable absorber section was modulated by an external signal with the cavity round trip frequency. Furthermore, the subharmonic mode-locking (SHML) technique alleviates the restrictions of high speed driving electronics. It has been demonstrated experimentally$^{(1)}$ that the hybrid subharmonic mode-locking technique has lead to significant reduction of the timing jitter. (omitted)